Self-Adaption of the GIDL Erase Promotes Stacking More Layers in 3D NAND Flash [PDF]
Micromachines, 2023 The bit density is generally increased by stacking more layers in 3D NAND Flash. Gate-induced drain leakage (GIDL) erase is a critical enabler in the future development of 3D NAND Flash.
Tao Yang
exaly +7 more sources
Incremental Pulse-Width Erase (IPWE) Scheme for Fast and Variation-Tolerant GIDL Erase of 3D NAND Flash [PDF]
MicromachinesIn this work, we propose an incremental pulse-width erase (IPWE) scheme for fast and variation-tolerant gate-induced drain leakage (GIDL) erase of 3D NAND flash.
Youngjun Park, Wonbo Shim
exaly +5 more sources
Small StructuresOxide semiconductors (OSs) are promising materials for NAND flash memory, offering the advantages of high field‐effect mobility and superior large‐area uniformity but suffering from low thermal stability, trade‐off between mobility and stability, and the
Yun Heub Song, Jin-Seong Park
exaly +4 more sources
Efficient Erase Operation by GIDL Current for 3D Structure FeFETs With Gate Stack Engineering and Compact Long-Term Retention Model [PDF]
IEEE Journal of the Electron Devices Society, 2022 We have fabricated junctionless N-type silicon-on-insulator (SOI) ferroelectric-HfO2 field effect transistors (FeFETs) with overlap and underlap structures between gate and drain/source regions to investigate the role of gate-induced-drain-leakage (GIDL)
Toshiro Hiramoto +2 more
exaly +4 more sources
Origin of the Temperature Dependence of Gate-Induced Drain Leakage-Assisted Erase in Three-Dimensional nand Flash Memories [PDF]
MicromachinesThrough detailed experimental and modeling activities, this paper investigates the origin of the temperature dependence of the Erase operation in 3D nand flash arrays.
David G. Refaldi +4 more
doaj +4 more sources
Optimal Bias Condition of Dummy WL for Sub-Block GIDL Erase Operation in 3D NAND Flash Memory
Electronics (Switzerland), 2022 In this study, we have analyzed the optimal bias condition of dummy WL for the sub-block gate induced drain leakage (GIDL) erase operation in 16-layer 3D NAND flash memory. Three-dimensional NAND flash memory performs an erase operation in units of pages.
Myounggon Kang
exaly +3 more sources
SiGe-Surrounded Bitline Structure for Enhancing 3D NAND Flash Erase Speed
Applied Sciences (Switzerland)Three-dimensional NAND Flash has adopted the cell-over-peripheral (COP) structure to increase storage density. Unlike the conventional structure, the COP structure cannot directly increase the channel potential via substrate bias during the erase ...
Wonbo Shim
exaly +4 more sources
Modeling of GIDL–Assisted Erase in 3–D NAND Flash Memory Arrays and Its Employment in NOR Flash–Based Spiking Neural Networks [PDF]
SpringerBriefs in Applied Sciences and Technology, 2022 AbstractSince the very first introduction of three-dimensional (3–D) vertical-channel (VC) NAND Flash memory arrays, gate-induced drain leakage (GIDL) current has been suggested as a solution to increase the string channel potential to trigger the erase operation. Thanks to that erase scheme, the memory array can be built directly on the top of a$$n^+$$
Gerardo Malavena
exaly +2 more sources
Concealable physical unclonable functions using vertical NAND flash memory [PDF]
Nature CommunicationsPhysical Unclonable Functions (PUFs) can address the demand for enhanced hardware security. Vertical NAND (V-NAND) flash memory is the most commercialized non-volatile memory.
Sung-Ho Park +5 more
doaj +2 more sources
Distinguishing capture cross-section parameter between GIDL erase compact model and TCAD
Japanese Journal of Applied Physics, 2021 Abstract A compact model of 3D NAND enables simulation at circuit- or system-level. Although a compact model for gate-induced-drain-leakage (GIDL)-assisted erase was proposed in a previous study, it is difficult to use practically because it has not been properly validated.
Kul Lee, Hyungcheol Shin
exaly +2 more sources