Results 1 to 10 of about 93 (56)

Self-Adaption of the GIDL Erase Promotes Stacking More Layers in 3D NAND Flash [PDF]

Micromachines, 2023
The bit density is generally increased by stacking more layers in 3D NAND Flash. Gate-induced drain leakage (GIDL) erase is a critical enabler in the future development of 3D NAND Flash.
Tao Yang, Bao Zhang, Zhiliang Xia
exaly   +7 more sources

Incremental Pulse-Width Erase (IPWE) Scheme for Fast and Variation-Tolerant GIDL Erase of 3D NAND Flash [PDF]

Micromachines
In this work, we propose an incremental pulse-width erase (IPWE) scheme for fast and variation-tolerant gate-induced drain leakage (GIDL) erase of 3D NAND flash.
Youngjun Park, Wonbo Shim
exaly   +5 more sources

Unveiling the Hybrid‐Channel (poly‐Si/IGO) Structure for 3D NAND Flash Memory for Improving the Cell Current and GIDL‐Assisted Erase Operation

Small Structures
Oxide semiconductors (OSs) are promising materials for NAND flash memory, offering the advantages of high field‐effect mobility and superior large‐area uniformity but suffering from low thermal stability, trade‐off between mobility and stability, and the
Taewon Hwang, Yun-Heub Song, Jin-Seong Park   +2 more
exaly   +4 more sources

Origin of the Temperature Dependence of Gate-Induced Drain Leakage-Assisted Erase in Three-Dimensional nand Flash Memories [PDF]

Micromachines
Through detailed experimental and modeling activities, this paper investigates the origin of the temperature dependence of the Erase operation in 3D nand flash arrays.
David G. Refaldi, Gerardo Malavena, Luca Chiavarone, Alessandro S. Spinelli, Christian Monzio Compagnoni   +4 more
doaj   +4 more sources

Efficient Erase Operation by GIDL Current for 3D Structure FeFETs With Gate Stack Engineering and Compact Long-Term Retention Model [PDF]

IEEE Journal of the Electron Devices Society, 2022
We have fabricated junctionless N-type silicon-on-insulator (SOI) ferroelectric-HfO2 field effect transistors (FeFETs) with overlap and underlap structures between gate and drain/source regions to investigate the role of gate-induced-drain-leakage (GIDL)
Fei Mo, Toshiro Hiramoto, Chun-Jung Su   +2 more
exaly   +4 more sources

Optimal Bias Condition of Dummy WL for Sub-Block GIDL Erase Operation in 3D NAND Flash Memory

Electronics (Switzerland), 2022
In this study, we have analyzed the optimal bias condition of dummy WL for the sub-block gate induced drain leakage (GIDL) erase operation in 16-layer 3D NAND flash memory. Three-dimensional NAND flash memory performs an erase operation in units of pages.
Myounggon Kang
exaly   +3 more sources

Concealable physical unclonable functions using vertical NAND flash memory [PDF]

Nature Communications
Physical Unclonable Functions (PUFs) can address the demand for enhanced hardware security. Vertical NAND (V-NAND) flash memory is the most commercialized non-volatile memory.
Sung-Ho Park, Ryun-Han Koo, Yeongheon Yang, Jiseong Im, Jonghyun Ko, Jong-Ho Lee   +5 more
doaj   +3 more sources

Self-Curable Synaptic Ferroelectric FET Arrays for Neuromorphic Convolutional Neural Network. [PDF]

Adv Sci (Weinh), 2023
The primary challenge that ferroelectric field‐effect transistors face is their vulnerability to the repeated program/erase cycle. To solve this issue, an efficient self‐curing method is presented. The proposed method successfully recovers synaptic fatigue damage, enhancing learning accuracy in the convolutional neural network.
Shin W, Im J, Koo RH, Kim J, Kwon KR, Kwon D, Kim JJ, Lee JH, Kwon D.   +8 more
europepmc   +2 more sources

Model-Inversion-Resistant Physical Unclonable Neural Network Using Vertical NAND Flash Memory. [PDF]

Adv Sci (Weinh)
Schematic and key features of the proposed forward‐forward physical unclonable neural network (FF‐PUNN), incorporating a concealable physical unclonable function (PUF) layer and forward‐forward (FF) learning. ABSTRACT The growing use of neural networks in privacy‐sensitive applications necessitates architectures that inherently protect both data and ...
Park SH, Koo RH, Ko J, Im J, Yang Y, Oh M, Shin D, Jung G, Lee JH.   +8 more
europepmc   +2 more sources

Modeling of GIDL–Assisted Erase in 3–D NAND Flash Memory Arrays and Its Employment in NOR Flash–Based Spiking Neural Networks [PDF]

SpringerBriefs in Applied Sciences and Technology, 2022
AbstractSince the very first introduction of three-dimensional (3–D) vertical-channel (VC) NAND Flash memory arrays, gate-induced drain leakage (GIDL) current has been suggested as a solution to increase the string channel potential to trigger the erase operation. Thanks to that erase scheme, the memory array can be built directly on the top of a$$n^+$$
Gerardo Malavena
exaly   +2 more sources