Results 11 to 20 of about 93 (56)
IEEE Access, 2023 When designing 3D V-NAND technologies with a gate induced drain leakage (GIDL) assisted erase scheme, many experiments must be conducted to determine the optimal GIDL design targets to achieve fast erase performance and secure yield characteristics ...
Yohan Kim, Soyoung Kim
doaj +2 more sources
Advancing the Frontiers of HfO<sub>2</sub>-Based Ferroelectric Memories: Innovative Concepts from Materials to Applications. [PDF]
Adv MaterHfO2‐based ferroelectric materials are promising for next‐generation memory technologies by providing outstanding performance aligning with data‐centric computing needs. This review details recent advancements in materials, devices, and integration for HfO2‐based memories, with the goal of identifying both the technological opportunities and remaining ...
Zhou Z +9 more
europepmc +2 more sources
Distinguishing capture cross-section parameter between GIDL erase compact model and TCAD
Japanese Journal of Applied Physics, 2021 Abstract A compact model of 3D NAND enables simulation at circuit- or system-level. Although a compact model for gate-induced-drain-leakage (GIDL)-assisted erase was proposed in a previous study, it is difficult to use practically because it has not been properly validated.
Hyungcheol Shin
exaly +2 more sources
SiGe-Surrounded Bitline Structure for Enhancing 3D NAND Flash Erase Speed
Applied SciencesThree-dimensional NAND Flash has adopted the cell-over-peripheral (COP) structure to increase storage density. Unlike the conventional structure, the COP structure cannot directly increase the channel potential via substrate bias during the erase ...
Dohyun Kim, Wonbo Shim
doaj +2 more sources
Dual-Doped Cylindrical Bit-Line Pad for High-Efficiency Bulk Erase in V-NAND Flash
IEEE AccessWe propose a novel dual-doped cylindrical bit-line (DDC-BL) pad structure for vertical NAND (V-NAND) flash memory to enable efficient bulk erase operation through direct hole injection.
Choasub Kim +4 more
doaj +2 more sources
Review of ferroelectric field‐effect transistors for three‐dimensional storage applications
Nano Select, Volume 2, Issue 6, Page 1187-1207, June 2021., 2021 The ideal hysteresis of the ferroelectric thin film for ferroelectric field effect transistor‐based 3‐dimensional storage devices. The navy‐colored solid curve represents the typical displacement field (Dfer) versus voltage (Vfer) hysteresis. The two vertical arrows indicate that only a small portion of the remanent polarization (Pr) is required for ...
Hyeon Woo Park +2 more
wiley +1 more source
, 2022 In this paper, a Silicon-Pillar (SP) structure, a new structure to improve the erase speed in the 3D NAND flash structure to which ferroelectric memory is applied, is proposed and verified.
Jae Kyeong Jeong +3 more
core +1 more source
, 2021 In this study, we developed a V-NAND with an improved IGZO-P type (IP) floating filler (FF) structure based on an IGZO channel verified in previous studies and demonstrated that it has a very fast erase speed through device simulation.
Jae Kyeong Jeong +4 more
core +1 more source
적층형 수직 낸드 플래시 메모리에서 1비트 지우기 구현 [PDF]
, 2023 학위논문(박사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2023. 2. 최우영.낸드 플래시 메모리는 비휘발성 메모리로 높은 집적도를 장점으로 가진다. 낸드 플래시 메모리는 좀 더 높은 집적도를 위해 하나의 셀에 더 많은 비트의 데이터를 저장하거나 채널을 수직으로 세운 적층형 수직 낸드 플래시 기술이 개발되었다. 제한된 쓰기/지우기 구간에 더 많은 비트의 데이터를 저장하기 위해서는 더 좁은 메모리 셀 문턱 전압 산포를 만드는 것이 필요하다.
유호남
core
A new GIDL erase compact model of 3D NAND flash memory with proper capture cross section
, 2022 학위논문(석사) -- 서울대학교대학원 : 공과대학 전기·정보공학부, 2022.2. 신형철.3차원 수직 channel 낸드 플래시 메모리는 bit density를 향상시키는 방향으로 진화되어왔다. 최근에는 3차원 낸드 플래시 메모리의 bit density를 더욱 향상시키기 위해 CMOS under array 구조가 사용된다.
이걸
core