Results 41 to 50 of about 93 (56)

3DNAND GIDL-Assisted Body Biasing for Erase Enabling CMOS under Array (CUA) Architecture

2017 IEEE International Memory Workshop (IMW), 2017
The Gate-Induce-Drain-Leakage (GIDL)-assisted body biasing for erase, which is a technique essential to enabling 3DNAND Flash CMOS Under Array architectures, has been extensively studied and successfully optimized to achieve high-performance, reliable erase operation.
Christian Caillat, Kevin Beaman, Andrew Bicksler, Elisa Camozzi, Tecla Ghilardi, Guangyu Huang, Haitao Liu, Yifen Liu, Duo Mao, Salil Mujumdar, Niccolo Righetti, Matt Ulrich, Chandru Venkatasubramanian, Xiangyu Yang, Akira Goda, Srivardhan Gowda, Henok Mebrahtu, Hiroyuki Sanda, Yu Yuwen, Randy Koval   +19 more
exaly   +3 more sources

Compact modeling of GIDL-assisted erase in 3-D NAND Flash strings

Journal of Computational Electronics, 2019
This paper presents a physics-based compact model able to describe the time dynamics of the erase operation in three-dimensional NAND Flash strings exploiting gate-induced drain leakage at the selector to increase the string potential. The model accurately reproduces all the main phases of the erase operation and allows to calculate the threshold ...
Gerardo Malavena, Aurelio Mannará, Andrea L Lacaita   +2 more
exaly   +3 more sources

High Mobility and GIDL Erase-Compatible Characteristics in Hybrid Channel (Poly-Si/IGO) for Ultrahigh 3D NAND Flash Memory Applications

ACS Applied Electronic Materials
In this paper, we propose a hybrid channel (HC) structure in which the poly-Si and indium gallium oxide (IGO) channels coexist to achieve high mobility and gate-induced-drain-leakage (GIDL) erase-compatible characteristics for 3D NAND flash memory ...
Jae-Min Sim, Su-Hwan Choi, Seong-Hwan Ryu   +2 more
exaly   +3 more sources

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Improvement of GIDL-assisted Erase by using Surrounded BL PAD Structure for VNAND

2023 IEEE International Memory Workshop (IMW), 2023
Sunghoi Hur, Jaehoon Jang, Jaihyuk Song   +2 more
exaly   +2 more sources

A Process-Aware Compact Model for GIDL-Assisted Erase Optimization of 3-D V-NAND Flash Memory

IEEE Transactions on Electron Devices, 2023
Yohan Kim, Soyoung Kim
exaly   +2 more sources

Analysis of Grain Boundary Effect in GIDL-erase-scheme Vertical CTF Strings for High Stacked CMOS under Array 3-D NAND Flash

Extended Abstracts of the 2022 International Conference on Solid State Devices and Materials, 2022
Moonkyu Song, Joe Friedman, Sanjay K. Banerjee   +2 more
exaly   +2 more sources

A Compact Model for GIDL-Assisted Erase Transients of 3D MONOS Charge-Trap NAND Flash Memories

2025 9th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)
Sungju Kim, Hyungcheol Shin
exaly   +2 more sources

Investigation of Hot Carrier Injection During GIDL Erase Operation in 3-D NAND Flash Memory

IEEE Transactions on Electron Devices
Jin Ho Chang, Jin Wook Lee, Suk-Kang Sung   +2 more
exaly   +2 more sources

Analysis of GIDL Erase Characteristics in Vertical NAND Flash Memory

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2023
Ho-Nam Yoo, Yeongheon Yang, Min-Kyu Park, Woo-Young Choi, Jong-Ho Lee   +4 more
openaire   +1 more source

Strategies to Improve Efficiency of Select-Gate Voltage Floating During GIDL-Assisted Erase in 3-D NAND Flash Memory

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Sungju Kim, Jaeyeop Jung, Hyungcheol Shin   +2 more
openaire   +1 more source