Results 41 to 50 of about 3,848,813 (157)

FinFETs: From Devices to Architectures

Advances in Electronics, Volume 2014, Issue 1, 2014., 2014
Since Moore’s law driven scaling of planar MOSFETs faces formidable challenges in the nanometer regime, FinFETs and Trigate FETs have emerged as their successors. Owing to the presence of multiple (two/three) gates, FinFETs/Trigate FETs are able to tackle short‐channel effects (SCEs) better than conventional planar MOSFETs at deeply scaled technology ...
Debajit Bhattacharya, Niraj K. Jha, Jaber Abu Qahouq   +2 more
wiley   +1 more source

The Impact of Gate-Induced Drain Leakage (GIDL) on Scaled MOSFETs for Low Power Device [PDF]

, 2018
In this research, we investigated the impact of Gate-Induced Drain Leakage (GIDL) on scaled Metal-OxideSemiconductor Field-Effect Transistor (MOSFET) for low power application.
Hanim, A.R.; Micro Nano Electronics (MiNE), Centre for Telecommunication Research and Innovation, Faculty of Electronics and Computer Engineering, Universiti Teknikal Malaysia Melaka, Hang Tuah Jaya, 76100 Durian Tunggal, Melaka, Malaysia., Mohd Zain, A.S.; Micro Nano Electronics (MiNE), Centre for Telecommunication Research and Innovation, Faculty of Electronics and Computer Engineering, Universiti Teknikal Malaysia Melaka, Hang Tuah Jaya, 76100 Durian Tunggal, Melaka, Malaysia., AH, AM; Micro Nano Electronics (MiNE), Centre for Telecommunication Research and Innovation, Faculty of Electronics and Computer Engineering, Universiti Teknikal Malaysia Melaka, Hang Tuah Jaya, 76100 Durian Tunggal, Melaka, Malaysia., Idris, S.K.; Micro Nano Electronics (MiNE), Centre for Telecommunication Research and Innovation, Faculty of Electronics and Computer Engineering, Universiti Teknikal Malaysia Melaka, Hang Tuah Jaya, 76100 Durian Tunggal, Melaka, Malaysia., Hazura, H.; Micro Nano Electronics (MiNE), Centre for Telecommunication Research and Innovation, Faculty of Electronics and Computer Engineering, Universiti Teknikal Malaysia Melaka, Hang Tuah Jaya, 76100 Durian Tunggal, Melaka, Malaysia., Ngelayang, T.B.; Micro Nano Electronics (MiNE), Centre for Telecommunication Research and Innovation, Faculty of Electronics and Computer Engineering, Universiti Teknikal Malaysia Melaka, Hang Tuah Jaya, 76100 Durian Tunggal, Melaka, Malaysia., Salehuddin, F.; Micro Nano Electronics (MiNE), Centre for Telecommunication Research and Innovation, Faculty of Electronics and Computer Engineering, Universiti Teknikal Malaysia Melaka, Hang Tuah Jaya, 76100 Durian Tunggal, Melaka, Malaysia.   +6 more
core  

Reduction of gate-induced drain leakage current of polycrystalline silicon thin-film transistor by drain bias sweeping

, 2015
Method of drain bias sweeping is reported to reduce the gate-induced drain leakage (GIDL) current but with other electrical parameters unaffected for p-type polycrystalline silicon thin-film transistors.
Wu, Yong, Huaisheng Wang, Dongli Zhang, Haiqin Zhou, Zhou, Haiqin, Mingxing Wang, Wang, Huaisheng, Wang, Mingxing, He, Jin, Yong Wu, Jin He, Zhang, Dongli   +11 more
core   +1 more source

In Materia Shaping of Randomness with a Standard Complementary Metal‐Oxide‐Semiconductor Transistor for Task‐Adaptive Entropy Generation

Advanced Functional Materials, Volume 36, Issue 23, 19 March 2026.
This study establishes a materials‐driven framework for entropy generation within standard CMOS technology. By electrically rebalancing gate‐oxide traps and Si‐channel defects in foundry‐fabricated FDSOI transistors, the work realizes in‐materia control of temporal correlation – achieving task adaptive entropy optimization for reinforcement learning ...
Been Kwak, Ryun‐Han Koo, Youngchan Cho, Changhyeon Han, Dongbin Kim, Soi Jeong, Yunho Shin, Joonhyeok Choi, Jiseong Im, Jonghyun Ko, Jong‐Ho Lee, Jangsaeng Kim, Youngho Kang, Wonjun Shin, Daewoong Kwon   +14 more
wiley   +1 more source

Modeling of the Channel Thickness Influence on Electrical Characteristics and Series Resistance in Gate‐Recessed Nanoscale SOI MOSFETs

Active and Passive Electronic Components, Volume 2013, Issue 1, 2013., 2013
Ultrathin body (UTB) and nanoscale body (NSB) SOI‐MOSFET devices, sharing a similar W/L but with a channel thickness of 46 nm and lower than 5 nm, respectively, were fabricated using a selective “gate‐recessed” process on the same silicon wafer. Their current‐voltage characteristics measured at room temperature were found to be surprisingly different ...
A. Karsenty, A. Chelly, Gerard Ghibaudo
wiley   +1 more source

Contribution of carrier tunneling and gate induced drain leakage effects to the gate and drain currents of fin-shaped field-effect transistors

, 2011
The contribution of carrier tunneling and gate induced drain leakage (GIDL) effects in the total gate and drain currents of FinFET devices with different dimensions is analyzed.
Estrada, M., Kilchytska, Valeriya, D. Flandre, Flandre, Denis, A. Cerdeira, Garduno, S.I., S. I. Garduño, M. Estrada, V. Kilchytska, Cerdeira, A., J. Alvarado, Alvarado, Jose Joaquin   +11 more
core   +1 more source

Dual-Doped Cylindrical Bit-Line Pad for High-Efficiency Bulk Erase in V-NAND Flash

IEEE Access
We propose a novel dual-doped cylindrical bit-line (DDC-BL) pad structure for vertical NAND (V-NAND) flash memory to enable efficient bulk erase operation through direct hole injection.
Choasub Kim, Jiwook Hong, Moonchurl Kim, Hyoungsub Kim, Jongwook Jeon   +4 more
doaj   +1 more source

An Innovative Indicator to Evaluate DRAM Cell Transistor Leakage Current Distribution

IEEE Journal of the Electron Devices Society, 2018
This paper is the first to propose an innovative method for measuring variations in dynamic random access memory (DRAM) cell transistors. Structural dispersion induces an extremely high cell leakage current, which determines aspects of DRAM performance ...
Min Hee Cho, Namho Jeon, Taek Yong Kim, Moonyoung Jeong, Sungsam Lee, Jong Seo Hong, Hyeong Sun Hong, Satoru Yamada   +7 more
doaj   +1 more source

1 Transistor‐Dynamic Random Access Memory as Synaptic Element for Online Learning

Advanced Intelligent Systems, Volume 7, Issue 8, August 2025.
This work demonstrates the feasibility of utilizing capacitor‐less 1 transistor(1 T)‐dynamic random access memory as synaptic element with multilevel capability, large dynamic range of conductance, high linearity, ultralow energy consumption, high endurance exceeding 1015 cycles, and large integration density for artificial‐intelligence‐of‐things edge ...
MD Yasir Bashir, Pritish Sharma, Shubham Sahay   +2 more
wiley   +1 more source

The 'gated-diode' configuration in MOSFET's, a sensitive tool for characterizing hot-carrier degradation [PDF]

, 1995
This paper describes a new measurement technique, the forward gated-diode current characterized at low drain voltages to be applied in MOSFET's for investigating hot-carrier stress-induced defects at high spatial resolution.
Speckbacher, P., Weber, W., Berger, J., Asenov, A., Koch, D.   +4 more
core   +1 more source