Results 41 to 50 of about 311 (157)

Dual-Doped Cylindrical Bit-Line Pad for High-Efficiency Bulk Erase in V-NAND Flash

IEEE Access
We propose a novel dual-doped cylindrical bit-line (DDC-BL) pad structure for vertical NAND (V-NAND) flash memory to enable efficient bulk erase operation through direct hole injection.
Choasub Kim, Jiwook Hong, Moonchurl Kim, Hyoungsub Kim, Jongwook Jeon   +4 more
doaj   +1 more source

An Innovative Indicator to Evaluate DRAM Cell Transistor Leakage Current Distribution

IEEE Journal of the Electron Devices Society, 2018
This paper is the first to propose an innovative method for measuring variations in dynamic random access memory (DRAM) cell transistors. Structural dispersion induces an extremely high cell leakage current, which determines aspects of DRAM performance ...
Min Hee Cho, Namho Jeon, Taek Yong Kim, Moonyoung Jeong, Sungsam Lee, Jong Seo Hong, Hyeong Sun Hong, Satoru Yamada   +7 more
doaj   +1 more source

In Materia Shaping of Randomness with a Standard Complementary Metal‐Oxide‐Semiconductor Transistor for Task‐Adaptive Entropy Generation

Advanced Functional Materials, Volume 36, Issue 23, 19 March 2026.
This study establishes a materials‐driven framework for entropy generation within standard CMOS technology. By electrically rebalancing gate‐oxide traps and Si‐channel defects in foundry‐fabricated FDSOI transistors, the work realizes in‐materia control of temporal correlation – achieving task adaptive entropy optimization for reinforcement learning ...
Been Kwak, Ryun‐Han Koo, Youngchan Cho, Changhyeon Han, Dongbin Kim, Soi Jeong, Yunho Shin, Joonhyeok Choi, Jiseong Im, Jonghyun Ko, Jong‐Ho Lee, Jangsaeng Kim, Youngho Kang, Wonjun Shin, Daewoong Kwon   +14 more
wiley   +1 more source

Modeling of the Channel Thickness Influence on Electrical Characteristics and Series Resistance in Gate‐Recessed Nanoscale SOI MOSFETs

Active and Passive Electronic Components, Volume 2013, Issue 1, 2013., 2013
Ultrathin body (UTB) and nanoscale body (NSB) SOI‐MOSFET devices, sharing a similar W/L but with a channel thickness of 46 nm and lower than 5 nm, respectively, were fabricated using a selective “gate‐recessed” process on the same silicon wafer. Their current‐voltage characteristics measured at room temperature were found to be surprisingly different ...
A. Karsenty, A. Chelly, Gerard Ghibaudo
wiley   +1 more source

Contribution of carrier tunneling and gate induced drain leakage effects to the gate and drain currents of fin-shaped field-effect transistors

, 2011
The contribution of carrier tunneling and gate induced drain leakage (GIDL) effects in the total gate and drain currents of FinFET devices with different dimensions is analyzed.
Estrada, M., Kilchytska, Valeriya, D. Flandre, Flandre, Denis, A. Cerdeira, Garduno, S.I., S. I. Garduño, M. Estrada, V. Kilchytska, Cerdeira, A., J. Alvarado, Alvarado, Jose Joaquin   +11 more
core   +1 more source

1 Transistor‐Dynamic Random Access Memory as Synaptic Element for Online Learning

Advanced Intelligent Systems, Volume 7, Issue 8, August 2025.
This work demonstrates the feasibility of utilizing capacitor‐less 1 transistor(1 T)‐dynamic random access memory as synaptic element with multilevel capability, large dynamic range of conductance, high linearity, ultralow energy consumption, high endurance exceeding 1015 cycles, and large integration density for artificial‐intelligence‐of‐things edge ...
MD Yasir Bashir, Pritish Sharma, Shubham Sahay   +2 more
wiley   +1 more source

Insight Into Gate-Induced Drain Leakage in Silicon Nanowire Transistors

, 2015
In this paper, detailed physical mechanisms of gate-induced drain leakage (GIDL) in gate-all-around silicon nanowire transistors (SNWTs) are investigated and verified by experiments and TCAD studies.
Li, Ming, Xuan, Haoran, Xu, Xiaoyan, Yang, Yuancheng, Fan, Jiewen, Huang, Ru   +5 more
core   +1 more source

Investigation of the Scalability of Emerging Nanotube Junctionless FETs Using an Intrinsic Pocket

IEEE Journal of the Electron Devices Society, 2019
The detrimental lateral band-to-band tunneling (L-BTBT) governing the OFF-state performance of the junctionless (JL) FETs is more pronounced in emerging Nanotube (NT) transistor architectures. This restricts the scaling of NT JLFETs irrespective of their
Aakash Kumar Jain, Jaspreet Singh, Mamidala Jagadesh Kumar   +2 more
doaj   +1 more source

Unveiling the Hybrid‐Channel (poly‐Si/IGO) Structure for 3D NAND Flash Memory for Improving the Cell Current and GIDL‐Assisted Erase Operation

Small Structures, Volume 6, Issue 5, May 2025.
A hybrid structure with heterostacked poly‐Si and In–Ga–O (IGO) is used as the channel layer of 3D NAND flash memory. IGO is used as the main channel to improve electrical properties and deviations while achieving high thermal stability. Poly‐Si is used to generate gate‐induced drain leakage current via band‐to‐band tunneling and thus enable the erase ...
Su‐Hwan Choi, Jae‐Min Sim, Jeongmin Shin, Seong‐Hwan Ryu, Taewon Hwang, So Young Lim, Hye‐Jin Oh, Jae‐Hyeok Kwag, Jun‐Yeoub Lee, Ki‐Cheol Song, Yeonhee Lee, Minju Song, Junghwan Kim, Chang‐Kyun Park, Yun‐Heub Song, Jin‐Seong Park   +15 more
wiley   +1 more source

Controlling L-BTBT in Emerging Nanotube FETs Using Dual-Material Gate

IEEE Journal of the Electron Devices Society, 2018
Nanotube (NT) FETs have been proposed as the most promising architecture for the ultimate scaling of FETs. However, an enhanced L-BTBT restricts their scaling.
Aakash Kumar Jain, Shubham Sahay, Mamidala Jagadesh Kumar   +2 more
doaj   +1 more source