Results 61 to 70 of about 3,848,813 (157)

SiGe-Surrounded Bitline Structure for Enhancing 3D NAND Flash Erase Speed

open access: yesApplied Sciences
Three-dimensional NAND Flash has adopted the cell-over-peripheral (COP) structure to increase storage density. Unlike the conventional structure, the COP structure cannot directly increase the channel potential via substrate bias during the erase ...
Dohyun Kim, Wonbo Shim
doaj   +1 more source

Analysis of Random Telegraph Noise after Soft Breakdown in the Gate Induced Drain Leakage Current [PDF]

open access: yes, 2013
학위논문 (석사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2013. 8. 신형철.A Random Telegraph Noise (RTN) in leakage current has been important for discovering the cause of Variable Retention Time (VRT) in Dynamic Random Access Memory (DRAM) cell transistor.
이슬기
core  

Characterization & Modeling of Gate-Induced-Drain-Leakage with complete overlap and fringing model

open access: yes
This paper investigates and models Gate Induced Drain Leakage (GIDL) for a wide variety of high voltage devices with different low doped drain (LDD) structures.
Jaouen, H.   +8 more
core   +1 more source

Mechanism analysis of gate-induced drain leakage in off-state n-MOSFET

open access: yes, 1997
An analytical expression for both band-to-band and band-trap-band indirect tunnelings is used to study the gate-induced drain leakage (GIDL) current of MOSFETs measured before and after hot-carrier stress.
J.P. Xu   +7 more
core   +1 more source

On the Conduction Mechanism in Diamond 2-D Hole Gas Field Effect Transistors

open access: yesIEEE Access
Diamond two-dimensional hole gas (2DHG) field-effect transistors are an emerging device class with significant practical potential. To date, hole mobility in such devices has been largely assessed using Hall effect measurements, with only limited ...
Andrew J. Walker   +3 more
doaj   +1 more source

A surface-potential-based compact model for partially-depleted silicon-on-insulator MOSFETs

open access: yes, 2009
With the continuous scaling of CMOS technologies, Silicon-on-Insulator (SOI) technologies have become more competitive compared to bulk, due to their lower parasitic capacitances and leakage currents. The shift towards high frequency, low power circuitry,
Benson, James
core   +1 more source

Correlation Between Gate Induced Drain Leakage and Plasma Induced Interface Traps

open access: yes, 1999
In this paper we carefully investigate the correlation between gate induced drain leakage current and plasma induced damages in the deep submicron p+ polysilicon gate pMOSFETs with gate oxide thickness of 50 Å. Low field enhancement of gate induced drain
M. F. Li   +6 more
core   +1 more source

GIDL behavior of p- and n-MuGFET devices with different TiN metal gate thickness and high-k gate dielectrics

open access: yes, 2012
This work studies the gate-induced drain leakage (GIDL) in p- and n-MuGFET structures with different TiN metal gate thickness and high-k gate dielectrics.
Rodrigues, M.   +11 more
core   +1 more source

Physics‐Based Compact Modeling of Advanced 3D Nanoscale Vertical NAND Flash Memory

open access: yesAdvanced Electronic Materials
The increasing complexity of 3‐dimensional (3D) NAND flash memory necessitates advanced simulation frameworks to predict read behavior, program/erase (P/E) dynamics, and interactions between neighboring cells.
Ilho Myeong, Seonho Shin, Ickhyun Song
doaj   +1 more source

A String-Select-Line Separation Patterning Scheme for Low Voltage and High-Speed Program Operation in 3D NAND Flash Memory With Separated Source-Line

open access: yesIEEE Access
In this paper, we propose a novel String-Select-Line Separation Patterning (SSP) scheme designed for low voltage and high-speed program operation in 3D NAND flash memory structures with a separated Source-Line (SL).
Jae-Min Sim, Hakyeong Kim, Yun-Heub Song
doaj   +1 more source

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