Results 11 to 20 of about 143 (115)

Suppressing Gate-Induced Drain Leakage with an Asymmetric Gate Design in HiPco CNT FETs [PDF]

Nanomaterials
Carbon nanotube field-effect transistors (CNT FETs) hold great promise for extending Moore’s Law, yet their performance is critically limited by excessive off-state leakage, caused by band-to-band tunneling (BTBT) in narrow bandgap CNT channels.
Hui Ma, Senbiao Gu, Minglong Zhai, Honggang Liu   +3 more
doaj   +2 more sources

Origin of the Temperature Dependence of Gate-Induced Drain Leakage-Assisted Erase in Three-Dimensional nand Flash Memories [PDF]

Micromachines
Through detailed experimental and modeling activities, this paper investigates the origin of the temperature dependence of the Erase operation in 3D nand flash arrays.
David G. Refaldi, Gerardo Malavena, Luca Chiavarone, Alessandro S. Spinelli, Christian Monzio Compagnoni   +4 more
doaj   +2 more sources

Stacked Nanosheet Gate-All-Around Morphotropic Phase Boundary Field-Effect Transistors. [PDF]

Adv Sci (Weinh)
This study proposes a material design using ferroelectric‐antiferroelectric mixed‐phase HZO to achieve steep subthreshold swing and non‐hysteretic on‐current enhancement in morphotropic phase boundary field‐effect transistors (MPB‐FETs). For the first time, two‐stacked nanosheet GAA MPB‐FETs with optimized HZO are demonstrated, validating superior ...
Kim S, Kim HM, Kwon KR, Kwon D.
europepmc   +2 more sources

A Novel Channel Preparation Scheme to Optimize Program Disturbance in Three-Dimensional NAND Flash Memory [PDF]

Micromachines
The program disturbance characteristics of three-dimensional (3D) vertical NAND flash cell array architecture pose a critical reliability challenge due to the lower unselected word line (WL) pass bias (Vpass) window. In other words, the key contradiction
Kaikai You, Lei Jin, Jianquan Jia, Zongliang Huo   +3 more
doaj   +2 more sources

Concealable physical unclonable functions using vertical NAND flash memory [PDF]

Nature Communications
Physical Unclonable Functions (PUFs) can address the demand for enhanced hardware security. Vertical NAND (V-NAND) flash memory is the most commercialized non-volatile memory.
Sung-Ho Park, Ryun-Han Koo, Yeongheon Yang, Jiseong Im, Jonghyun Ko, Jong-Ho Lee   +5 more
doaj   +2 more sources

Advancing the Frontiers of HfO₂-Based Ferroelectric Memories: Innovative Concepts from Materials to Applications. [PDF]

Adv Mater
HfO2‐based ferroelectric materials are promising for next‐generation memory technologies by providing outstanding performance aligning with data‐centric computing needs. This review details recent advancements in materials, devices, and integration for HfO2‐based memories, with the goal of identifying both the technological opportunities and remaining ...
Zhou Z, Li L, Feng Y, Wang X, Zheng Z, Jiao L, Zheng H, Shi Y, Ang KW, Gong X.   +9 more
europepmc   +2 more sources

Improving the Gate-Induced Drain Leakage and On-State Current of Fin-Like Thin Film Transistors with a Wide Drain

Applied Sciences, 2018
Polycrystalline silicon (poly-Si) thin film transistors (TFT) with a tri-gate fin-like structure and wide drain were designed and simulated to improve gate-induced drain leakage (GIDL), ON-state current, and breakdown voltage.
Hsin-Hui Hu, Yan-Wei Zeng, Kun-Ming Chen
doaj   +3 more sources

Efficient Erase Operation by GIDL Current for 3D Structure FeFETs With Gate Stack Engineering and Compact Long-Term Retention Model

IEEE Journal of the Electron Devices Society, 2022
We have fabricated junctionless N-type silicon-on-insulator (SOI) ferroelectric-HfO2 field effect transistors (FeFETs) with overlap and underlap structures between gate and drain/source regions to investigate the role of gate-induced-drain-leakage (GIDL)
Fei Mo, Jiawen Xiang, Xiaoran Mei, Yoshiki Sawabe, Takuya Saraya, Toshiro Hiramoto, Chun-Jung Su, Vita Pi-Ho Hu, Masaharu Kobayashi   +8 more
doaj   +1 more source

Design impact on three gate Dynamic Flash Memory (3G_DFM) for long hole retention time and robust disturbance shield

Memories - Materials, Devices, Circuits and Systems, 2023
TCAD simulation using Silvaco software has shown that the 3G_DFM, which has SG1 (Select Gate 1), PL (Plate Line Gate), and SG2 (Select Gate 2) between SL (Source Line) and BL (Bit Line), has a long retention time of 100ms at 85 °C, and a robust ...
Koji Sakui, Yisuo Li, Masakazu Kakumu, Kenichi Kanazawa, Iwao Kunishima, Yoshihisa Iwata, Nozomu Harada   +6 more
doaj   +1 more source

Narrow Sub-Fin Technique for Suppressing Parasitic-Channel Effect in Stacked Nanosheet Transistors

IEEE Journal of the Electron Devices Society, 2022
A new approach of narrowing sub-fin with little extra process cost for suppressing parasitic-channel-effect (PCE) on vertically-stacked horizontal gate-all-around (GAA) Si nanosheet field-effect-transistors (NS-FETs) is proposed.
Jie Gu, Qingzhu Zhang, Zhenhua Wu, Yanna Luo, Lei Cao, Yuwei Cai, Jiaxin Yao, Zhaohao Zhang, Gaobo Xu, Huaxiang Yin, Jun Luo, Wenwu Wang   +11 more
doaj   +1 more source