Results 141 to 150 of about 2,685 (171)

Analysis of the Gate-Induced Drain Leakage of SOI Nanowire and Nanosheet MOS Transistors at High Temperatures

2022 IEEE Latin American Electron Devices Conference (LAEDC), 2022
This work presents a comparison between the Gate-Induced Drain Leakage (GIDL) current of the nanowire (tri-gate MOSFET with narrow fin width) and nanosheet (tri-gate MOSFET with wide fin width) SOI MOSFETs at high temperatures, in the range between 300 K
M. de Souza, A. Cerdeira, M. Estrada, S. Barraud, M. Cassé, M. Vinet, O. Faynot, M. Pavanello   +7 more
semanticscholar   +1 more source

Dual metal (DM) Insulated Shallow Extension (ISE) Gate All Around (GAA) MOSFET to reduce gate induced drain leakages (GIDL) for improved analog performance

2017 Devices for Integrated Circuit (DevIC), 2017
In this paper a Dual Metal Insulated Shallow Extension Gate All Around (DMISEGAA) MOSFET has been proposed to solve a big issue of Gate Inducted Drain leakage (GIDL) current in cylindrical Gate All Around (GAA) MOSFET for improved analog performance. DMISEGAA MOSFET improves gate leakages by minimizing the tunneling from Valence Band to Conduction Band
Sonam Rewari, Vandana Nath, Subhasis Haldar, S. S. Deswal, R. S. Gupta   +4 more
openaire   +1 more source

Analytical Model for Gate-Induced Drain Leakage Current Degradation in Polycrystalline Silicon Thin-Film Transistors Under DC Drain Voltage Stress

IEEE Transactions on Electron Devices
An analytical degradation model for gate-induced drain leakage current ( ${I} _{\text {GIDL}}$ ) in polycrystalline silicon thin-film transistors (TFTs) under dc drain bias stress is proposed for the first time in this work.
Yiming Song, Meng Zhang, Zhendong Jiang, Man Wong, H. Kwok   +4 more
semanticscholar   +1 more source

Modeling of Gate-Induced-Drain-Leakage Under Low Electric Field in FDSOI MOSFETs

IEEE Transactions on Electron Devices
In this study, we investigate and model gate-induced-drain-leakage (GIDL) in fully depleted silicon-on-insulator (FDSOI) MOSFETs under low electric fields.
Nisha Manzoor, Debashish Nandi, Chetan Kumar Dabhi, Aloke K. Dutta, Yogesh Singh Chauhan   +4 more
semanticscholar   +1 more source

Suppression of Gate-Induced-Drain-Leakage Utilizing Local Polarization in Ferroelectric-Gate Field-Effect Transistors for DRAM Applications

IEEE Electron Device Letters
This study proposed a novel approach to enhance the retention characteristics in dynamic random access memory (DRAM) by employing a unique local polarization method, attempting to increase the threshold voltage ( ${V}_{{\text {th}}}$ ) to reduce ...
Been Kwak, Kitae Lee, Sihyun Kim, Daewoong Kwon   +3 more
semanticscholar   +1 more source

A comprehensive study of gate-induced drain leakage current and electrical characteristics in nanosheet field-effect transistors due to variation in structural parameters and ambient temperature

Semiconductor Science and Technology
In this paper, two substrate optimization approaches for triple stacked nanosheet field-effect transistors (SNSHFETs), namely the optimization of buried oxide and the selective deposition of punch-through-stopper (PTS) substrate, have been examined, and ...
Shubham, Shruti Bhosle, R. K. Pandey
semanticscholar   +1 more source

Revisiting Lateral-BTBT Gate-Induced Drain Leakage in Nanowire FETs for 1T-DRAM

IEEE Transactions on Electron Devices
In this work, we revisit the lateral band-to-band tunneling (L-BTBT) gate-induced drain leakage (GIDL) in gate-all-around (GAA) nanowire field-effect transistors (NWFETs) which is otherwise detrimental to logic operation and propose design guidelines for
MD. Yasir Bashir, Anupam Kumar Jaiswal, Sharang Dhar Patel, Shubham Sahay   +3 more
semanticscholar   +1 more source

A Multi-WL Approach to Suppress Gate-Induced Drain Leakage, Floating Body Effect, and Row Hammer Effect in Array Transistor of 4F2 DRAM and 3D Stackable DRAM

International Electron Devices Meeting
Targeting the next-generation 4F2 DRAM and 3D stackable DRAM, we propose a multi-wordline (preferably 2-wordline) array transistor for 1T1C DRAM to efficiently minimize gate-induced drain leakage (GIDL), floating-body effect (FBE), and row hammer effect (
Wei-Chen Chen, H. Lue, Ming-Hung Wu, Xi-Wei Lin, Ko-Hsin Lee, Po-Chou Chen, Salvatore M. Amoroso, Keh-Chung Wang, Chih-Yuan Lu   +8 more
semanticscholar   +1 more source

Mechanism Study of Hot Carrier Degradation Recovery by Gate Induced Drain Leakage in 14 nm nFinFET

IEEE Electron Device Letters
In this study, a distinct recovery behavior in Hot Carrier Degradation (HCD), facilitated by Gate Induced Drain Leakage (GIDL), is observed in multi-fin nFinFET devices fabricated on 300 mm wafers using 16/14 nm technology.
Xianghui Li, Yi Gu, Chen Wang, Kun-hsein Chen, Xin Chao, Yafen Yang, Chengkang Tang, Hao Zhu, Q. Sun, David Wei Zhang   +9 more
semanticscholar   +1 more source

Solution-processed green and blue quantum-dot light-emitting diodes with eliminated charge leakage

Nature Photonics, 2022
Yunzhou Deng, Jing Qiu, Dawei Di
exaly