Results 11 to 20 of about 2,685 (171)

Concealable physical unclonable functions using vertical NAND flash memory [PDF]

Nature Communications
Physical Unclonable Functions (PUFs) can address the demand for enhanced hardware security. Vertical NAND (V-NAND) flash memory is the most commercialized non-volatile memory.
Sung-Ho Park, Ryun-Han Koo, Yeongheon Yang, Jiseong Im, Jonghyun Ko, Jong-Ho Lee   +5 more
doaj   +2 more sources

Investigation of Gate-Induced Drain Leakage (GIDL) Current in Thin Body Devices: Single-Gate Ultra-Thin Body, Symmetrical Double-Gate, and Asymmetrical Double-Gate MOSFETs

Japanese Journal of Applied Physics, 2003
Gate-induced drain leakage (GIDL) current is investigated in single-gate (SG) ultra-thin body field effect transistor (FET), symmetrical double-gate (DG) FinFET, and asymmetrical DG metal oxide semiconductor field effect transistor (MOSFET) devices. Measured reductions in GIDL current for SG and DG thin-body devices are reported for the first time. The
Choi, YK Choi, Yang-Kyu, Ha, D, King, TJ, Bokor, J   +3 more
openaire   +2 more sources

Effects of Externally Applied Uniaxial Tensile Stress on Gate Induced Drain Leakage (GIDL) Current of Metal-Oxide-Semiconductor Transistors

ECS Meeting Abstracts, 2011
Abstract not Available.
W. Lau
openaire   +2 more sources

Self-Curable Synaptic Ferroelectric FET Arrays for Neuromorphic Convolutional Neural Network. [PDF]

Adv Sci (Weinh), 2023
The primary challenge that ferroelectric field‐effect transistors face is their vulnerability to the repeated program/erase cycle. To solve this issue, an efficient self‐curing method is presented. The proposed method successfully recovers synaptic fatigue damage, enhancing learning accuracy in the convolutional neural network.
Shin W, Im J, Koo RH, Kim J, Kwon KR, Kwon D, Kim JJ, Lee JH, Kwon D.   +8 more
europepmc   +2 more sources

Stacked Nanosheet Gate-All-Around Morphotropic Phase Boundary Field-Effect Transistors. [PDF]

Adv Sci (Weinh)
This study proposes a material design using ferroelectric‐antiferroelectric mixed‐phase HZO to achieve steep subthreshold swing and non‐hysteretic on‐current enhancement in morphotropic phase boundary field‐effect transistors (MPB‐FETs). For the first time, two‐stacked nanosheet GAA MPB‐FETs with optimized HZO are demonstrated, validating superior ...
Kim S, Kim HM, Kwon KR, Kwon D.
europepmc   +2 more sources

Advancing the Frontiers of HfO₂-Based Ferroelectric Memories: Innovative Concepts from Materials to Applications. [PDF]

Adv Mater
HfO2‐based ferroelectric materials are promising for next‐generation memory technologies by providing outstanding performance aligning with data‐centric computing needs. This review details recent advancements in materials, devices, and integration for HfO2‐based memories, with the goal of identifying both the technological opportunities and remaining ...
Zhou Z, Li L, Feng Y, Wang X, Zheng Z, Jiao L, Zheng H, Shi Y, Ang KW, Gong X.   +9 more
europepmc   +2 more sources

Efficient Erase Operation by GIDL Current for 3D Structure FeFETs With Gate Stack Engineering and Compact Long-Term Retention Model

IEEE Journal of the Electron Devices Society, 2022
We have fabricated junctionless N-type silicon-on-insulator (SOI) ferroelectric-HfO2 field effect transistors (FeFETs) with overlap and underlap structures between gate and drain/source regions to investigate the role of gate-induced-drain-leakage (GIDL)
Fei Mo, Jiawen Xiang, Xiaoran Mei, Yoshiki Sawabe, Takuya Saraya, Toshiro Hiramoto, Chun-Jung Su, Vita Pi-Ho Hu, Masaharu Kobayashi   +8 more
doaj   +1 more source

Design impact on three gate Dynamic Flash Memory (3G_DFM) for long hole retention time and robust disturbance shield

Memories - Materials, Devices, Circuits and Systems, 2023
TCAD simulation using Silvaco software has shown that the 3G_DFM, which has SG1 (Select Gate 1), PL (Plate Line Gate), and SG2 (Select Gate 2) between SL (Source Line) and BL (Bit Line), has a long retention time of 100ms at 85 °C, and a robust ...
Koji Sakui, Yisuo Li, Masakazu Kakumu, Kenichi Kanazawa, Iwao Kunishima, Yoshihisa Iwata, Nozomu Harada   +6 more
doaj   +1 more source

Narrow Sub-Fin Technique for Suppressing Parasitic-Channel Effect in Stacked Nanosheet Transistors

IEEE Journal of the Electron Devices Society, 2022
A new approach of narrowing sub-fin with little extra process cost for suppressing parasitic-channel-effect (PCE) on vertically-stacked horizontal gate-all-around (GAA) Si nanosheet field-effect-transistors (NS-FETs) is proposed.
Jie Gu, Qingzhu Zhang, Zhenhua Wu, Yanna Luo, Lei Cao, Yuwei Cai, Jiaxin Yao, Zhaohao Zhang, Gaobo Xu, Huaxiang Yin, Jun Luo, Wenwu Wang   +11 more
doaj   +1 more source

Emerging reconfigurable electronic devices based on two‐dimensional materials: A review

InfoMat, Volume 4, Issue 10, October 2022., 2022
An intense survey of novel reconfigurable devices based on 2D materials is presented with a focus on reconfigurable transistors that offer run‐time control of charge carriers, threshold voltage, and subthreshold swing, and reconfigurable heterostructures manifested as multiple device configurations in one device. The working principles of these devices
Wenwen Fei, Jens Trommer, Max Christian Lemme, Thomas Mikolajick, André Heinzig   +4 more
wiley   +1 more source