Results 21 to 30 of about 2,685 (171)
Mathematical Modeling and Performance Evaluation of 3D Ferroelectric Negative Capacitance FinFET
Modelling and Simulation in Engineering, Volume 2022, Issue 1, 2022., 2022 Ferroelectric negative capacitance materials have now been proposed for lowering electronics energy dissipation beyond basic limitations. In this paper, we presented the analysis on the performance of negative capacitance (NC) FinFET in comparison with conventional gate dielectrics by using a separation of variables approach, which is an optimal quasi ...
Sayem Ul Alam +6 more
wiley +1 more source
Review of ferroelectric field‐effect transistors for three‐dimensional storage applications
Nano Select, Volume 2, Issue 6, Page 1187-1207, June 2021., 2021 The ideal hysteresis of the ferroelectric thin film for ferroelectric field effect transistor‐based 3‐dimensional storage devices. The navy‐colored solid curve represents the typical displacement field (Dfer) versus voltage (Vfer) hysteresis. The two vertical arrows indicate that only a small portion of the remanent polarization (Pr) is required for ...
Hyeon Woo Park +2 more
wiley +1 more source
Thermal synergies in 50 nanometer CMOS and below
IET Circuits, Devices &Systems, Volume 15, Issue 2, Page 183-196, March 2021., 2021 Abstract An analysis of the metal oxide semiconductor field effect transistor (MOSFET) in strong inversion indicates two bias regions, in each of its triode and saturation conditions, whose distinct properties are elaborated and shown to lead to simple, systematic, design procedures for achieving low temperature coefficient (TC) voltages (<±100 ppm/°C)
F.S. Shoucair
wiley +1 more source
IEEE Access, 2023 When designing 3D V-NAND technologies with a gate induced drain leakage (GIDL) assisted erase scheme, many experiments must be conducted to determine the optimal GIDL design targets to achieve fast erase performance and secure yield characteristics ...
Yohan Kim, Soyoung Kim
doaj +1 more source
Applied Sciences, 2018 Polycrystalline silicon (poly-Si) thin film transistors (TFT) with a tri-gate fin-like structure and wide drain were designed and simulated to improve gate-induced drain leakage (GIDL), ON-state current, and breakdown voltage.
Hsin-Hui Hu, Yan-Wei Zeng, Kun-Ming Chen
doaj +1 more source
Enhanced off-state leakage currents in n-channel MOSFET's with N2O-grown gate dielectric [PDF]
, 1995 This paper reports on the off-state drain (GIDL) and gate current (Ig) characteristics of n-channel MOSFETs using thin thermal oxide (OX), N2O-nitrided oxide (N2ON), and N2O-grown oxide (N20G) as gate dielectrics.
Lai, PT, Ng, WT, Xu, Z
core +1 more source
Generic radiation hardened photodiode layouts for deep submicron CMOS image sensor processes [PDF]
, 2011 Selected radiation hardened photodiode layouts, manufactured in a deep submicron CMOS Image Sensor technology, are irradiated by 60Co gamma-rays up to 2.2 Mrad(SiO2) and studied in order to identify the most efficient structures and the guidelines ...
Cervantes, Paola +5 more
core +1 more source
IEEE Access, 2017 In this paper, we have performed a comprehensive analysis of the gate-induced drain leakage (GIDL) in emerging nanotube (NT) and nanowire (NW) FET architectures.
Shubham Sahay, Mamidala Jagadesh Kumar
doaj +1 more source
Correlation between hot-carrier-induced interface states and GIDL current increase in N-MOSFET's [PDF]
, 1998 Correlation between created interface states and GIDL current increase in n-MOSFET's during hot-carrier stress is quantitatively discussed. A trap-assisted two-step tunneling model is used to relate the increased interface-state density (ADH) with the ...
Cheng, YC +4 more
core +1 more source
Interface-state-induced degradation of GIDL current in n-MOSFETsunder hot-carrier stress [PDF]
, 1996 The dependence of increase in post-stress gate-induced-drain-leakage (GIDL) current in n-MOSFET's on creation of interface states (ΔDit) during hot-carrier stress with VG = 0.5 VD was investigated.
Lai, PT, Liu, BY, Xu, JP, Zeng, X
core +1 more source