Results 51 to 60 of about 2,685 (171)
Architectures and Arithmetic for Low Static Power Consumption in Nanoscale CMOS
VLSI Design, Volume 2009, Issue 1, 2009., 2009 This paper focuses on leakage reduction at architecture and arithmetic level. A methodology for considerable reduction of the static power consumption is shown. Simulations are done in a typical 130 nm CMOS technology. Based on the simulation results, the static power consumption is estimated and compared for different filter architectures. Substantial
Peter Nilsson, Israel Koren
wiley +1 more source
Investigation of the Scalability of Emerging Nanotube Junctionless FETs Using an Intrinsic Pocket
IEEE Journal of the Electron Devices Society, 2019 The detrimental lateral band-to-band tunneling (L-BTBT) governing the OFF-state performance of the junctionless (JL) FETs is more pronounced in emerging Nanotube (NT) transistor architectures. This restricts the scaling of NT JLFETs irrespective of their
Aakash Kumar Jain +2 more
doaj +1 more source
Effect of Reverse Body Bias on Current Testing of 0.18 μm Gates
VLSI Design, Volume 12, Issue 4, Page 501-513, 2001., 2001 Systematic investigations on defect‐free IDDQ in deep submicron CMOS with reverse body bias were performed by SPICE simulation towards an attempt to improve resolution of IDDQ measurement. Effects of reverse body bias on off‐state leakage of scaled CMOS devices and IDDQ of typical CMOS circuit cells were investigated.
Xiaomei Liu, Prachi Sathe, Samiha Mourad
wiley +1 more source
Controlling L-BTBT in Emerging Nanotube FETs Using Dual-Material Gate
IEEE Journal of the Electron Devices Society, 2018 Nanotube (NT) FETs have been proposed as the most promising architecture for the ultimate scaling of FETs. However, an enhanced L-BTBT restricts their scaling.
Aakash Kumar Jain +2 more
doaj +1 more source
Small Structures, Volume 6, Issue 5, May 2025.A hybrid structure with heterostacked poly‐Si and In–Ga–O (IGO) is used as the channel layer of 3D NAND flash memory. IGO is used as the main channel to improve electrical properties and deviations while achieving high thermal stability. Poly‐Si is used to generate gate‐induced drain leakage current via band‐to‐band tunneling and thus enable the erase ...
Su‐Hwan Choi +15 more
wiley +1 more source
Enhancing Device Performance with High Electron Mobility GeSn Materials
Advanced Electronic Materials, Volume 11, Issue 5, April 2025.Vertical gate‐all‐around nanowire n‐FETs based on GeSn‐alloys with Sn‐contents of 8% and 11% are presented. A great improvement in Ion, gm, and SS is found with increased Sn‐content. A fivefold increase in on‐current is observed for 11%‐GeSn compared to Ge, underlining the potential of GeSn for nanoelectronics applications.
Yannik Junk +10 more
wiley +1 more source
Nonlinear Variation Decomposition of Neural Networks for Holistic Semiconductor Process Monitoring
Advanced Intelligent Systems, Volume 6, Issue 10, October 2024.The nonlinear variation decomposition is proposed to decompose output variations from neural network inputs and to evaluate the influence of unit processes in each sample from semiconductor manufacturing. Herein, industrial 1Y nm node dynamic random‐access memory test vehicles with baseline and split tests introducing high‐k metal gates with a minimum ...
Hyeok Yun +11 more
wiley +1 more source
Lateral Migration‐based Flash‐like Synaptic Device for Hybrid Off‐chip/On‐chip Training
Advanced Electronic Materials, Volume 10, Issue 4, April 2024.The first‐ever engineering application of lateral migration in charge trap memory, which is perceived as a disadvantage in the memory industry, is proposed to achieve low‐power operation while maintaining superior retention and improving endurance. By varying the length of tunneling oxide, the proposed device diverges from conventional techniques in ...
Min‐Kyu Park +6 more
wiley +1 more source
A new circuit technique for reduced leakage current in Deep Submicron CMOS technologies [PDF]
, 2005 Modern CMOS processes in the Deep Submicron regime are restricted to supply voltages below 2 volts and further to account for the transistors' field strength limitations and to reduce the power per logic gate.
A. Schmitz, A. Schmitz, R. Tielert
core
Silicon-compatible high-hole-mobility transistor with an undoped germanium channel for low-power application [PDF]
, 2013 In this work, Ge-based high-hole-mobility transistor with Si compatibility is designed, and its performance is evaluated. A 2-dimensional hole gas is effectively constructed by a AlGaAs/Ge/Si heterojunction with a sufficiently large valence band offset ...
Cho, Seongjae +4 more
core +1 more source