Results 71 to 80 of about 301 (157)

Potential of a Sensitive Silicon Mechanical Stress Sensor Based on a Change in Gate-Induced-Drain Leakage Current

, 2011
Mechanical stress sensors based on silicon piezoresistance have limited sensitivity. Mechanical stress sensors based on the on-current or off-current or threshold voltage of silicon MOS transistors also have limited sensitivity.
S.Y. Siah, Peizhen Yang, L. Chan, Wai S. Lau, V. Ho   +4 more
core   +1 more source

THE LOCAL THERMAL ANNEALING METHOD FOR CURING OF GATE OXIDE DAMAGE UTILIZING GATE-INDUCED DRAIN LEAKAGE CURRENT IN MOSFET

, 2020
게이트-유발 드레인 누설 전류를 활용한 전계효과 트랜지스터의 게이트 절연막 손상을 치유하는 방법이 개시된다. 본 발명의 일 실시예에 따른 트랜지스터의 열처리 방법은 트랜지스터의 열처리 방법에 있어서, 상기 트랜지스터의 게이트 전극과 드레인 전극 사이에 복구 전압을 인가하는 단계; 상기 복구 전압을 이용하여 소스 전극과 상기 드레인 전극 사이에 형성된 채널 영역에 게이트-유발 드레인 누설 전류(GIDL; gate-induced drain leakage ...
최양규, 박준영, 윤대환
core  

Charge injection using gate-induced-drain-leakage current for characterization of plasma edge damage in CMOS devices

, 1998
In this paper, we describe the application of gate-induced-drain-leakage (GIDL) current for the characterization of gate edge damage which occurs during the plasma etch processes.
Rao, V. R., SRIDHARAN, A, Chan, Y. D., Brozek, T., BROZEK, T, CHAN, YD, WERKING, JD, Viswanathan, C. R., RAMGOPAL RAO, V, Werking, J. D., VISWANATHAN, CR, Sridharan, A.   +11 more
core   +1 more source

Accurate leakage current models for MOSFET nanoscale devices

, 2020
This paper underlines a closed forms of MOSFET transistor’sleakage current mechanisms inthe sub 100nmparadigm.The incorporation of draininduced barrier lowering (DIBL), Gate Induced Drain Lowering (GIDL) and body effect (m) on the sub-threshold leakage ...
Mistarihi, Mamoun, Mamoun Al-Mistarihi, Rjoub, Abdoul, Abdoul Rjoub, Taradeh, Nedal Al, Nedal Al Taradeh   +5 more
core   +1 more source

Comprehensive evaluation of gate-induced drain leakage in SOI stacked nanowire nMOSFETs operating in high-temperatures

International audienceThis paper presents a comprehensive experimental analysis of the gate-induced drain leakage (GIDL) in two-level stacked nanowire SOI nMOSFETs for operating temperatures between 300 K and 580 K. Devices with different channel lengths
Vinet, Maud, Barraud, Sylvain, Cassé, Mikaël, de Souza, Michelly, Faynot, Olivier, Pavanello, Marcelo, Cerdeira, Antonio, Estrada, Magali   +7 more
core   +1 more source

Trap Depth Extraction using New Equation considering Tunneling Mechanism in Gate-Induced Drain Leakage Random Telegraph Noise [PDF]

, 2013
학위논문 (석사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2013. 2. 신형철.As device continue to scale down, the effect of an individual defect on device performance and reliability becomes important issue.
박슬기
core  

The role of a tensile stress bias for a sensitive silicon mechanical stress sensor based on a change in gate-induced-drain leakage current

, 2012
Mechanical stress sensors based on silicon piezoresistance have limited sensitivity. Mechanical stress sensors based on the on-current or off-current or threshold voltage of silicon MOS transistors also have limited sensitivity.
Lau, W. S., Yang, Peizhen., Chan, L., Siah, S. Y.   +3 more
core   +1 more source

New observation and improvement in GIDL of n-MOSFETs with various kinds of N2O-based gate oxides under hot-carrier stress

, 1996
Degradation in gate-induced drain leakage (GIDL) of n-MOSFETs with various kinds of gate oxides under hot-carrier stress at different gate voltages is investigated. It has been found that the shift of GIDL current is very sensitive to gate voltage and is
Xu, J, Lai, PT, Zeng, X, Cheng, YC
core   +1 more source

DRAM 셀 트렌지스터의 GIDL RTN에 의한 산화막 트랩의 위치 의존성 분석 [PDF]

, 2014
학위논문 (석사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2014. 2. Shin Hyungcheol.As device dimensions are minimized, random telegraph noise (RTN) is dominant in determining the performance and reliability of metal-oxide-semiconductor field effect transistor (MOSFET).
콴뉴엔기아
core  

Enhanced degradation of n-MOSFETs with high-k/metal gate stacks under channel hot-carrier/gate-induced drain leakage alternating stress

, 2018
Enhanced degradation of n-MOSFETs with high-k/metal gate stacks under CHC/GIDL alternating stress is investigated. CHC stress generates negative oxide charges while GIDL stress generates positive oxide charges in the gate oxide near drain region.
Kim, D, Kim, C, Kang, B, Park, J, Lee, S, Lee, C   +5 more
core   +1 more source