Inductive line tunneling FET using epitaxial tunnel layer with Ge-source and charge enhancement insulation. [PDF]
Discov Nano, 2023 Lin JT, Chang YC.
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The understanding of the impact of efficiently optimized underlap length on analog/RF performance parameters of GNR-FETs. [PDF]
Sci Rep, 2023 Ahmad MA, Kumar J.
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Simulation Study: The Impact of Structural Variations on the Characteristics of a Buried-Channel-Array Transistor (BCAT) in DRAM. [PDF]
Micromachines (Basel), 2022 Sun M, Baac HW, Shin C.
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, 1997 Degradation in gate-induced drain leakage (GIDL) current of n-MOSFET's with conventional SiO2 and oxynitride as gate dielectrics under hot-carrier stresses at different gate voltages is investigated.
Lai, PT +3 more
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Investigation of Erase Cycling Induced Joint Dummy Cell Disturbance in Dual-Deck 3D NAND Flash Memory. [PDF]
Micromachines (Basel), 2023 You K, Jin L, Jia J, Huo Z.
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Leakage scaling in deep submicron CMOS for SoC
, 2020 [[abstract]]In this paper, we demonstrate the effects of CMOS technology scaling on the high temperature characteristics (from 25 degreesC to 125 degreesC of the four components of off-state drain leakage (I-off) [i.e., subthreshold leakage (I-sub), gate
林佑昇, Lin, YS
core
N-Type Nanosheet FETs without Ground Plane Region for Process Simplification. [PDF]
Micromachines (Basel), 2022 Lee KS, Park JY.
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Mathematical Modeling of Drain Current Estimation in a CSDG MOSFET, Based on La2O3 Oxide Layer with Fabrication-A Nanomaterial Approach. [PDF]
Nanomaterials (Basel), 2022 Gowthaman N, Srivastava VM.
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Effects of Poly-Si Grain Boundary on Retention Characteristics under Cross-Temperature Conditions in 3-D NAND Flash Memory. [PDF]
Micromachines (Basel), 2023 An U +6 more
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SRAM Cell Design Challenges in Modern Deep Sub-Micron Technologies: An Overview. [PDF]
Micromachines (Basel), 2022 Gul W, Shams M, Al-Khalili D.
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