Results 91 to 100 of about 3,848,811 (155)

Effects of Poly-Si Grain Boundary on Retention Characteristics under Cross-Temperature Conditions in 3-D NAND Flash Memory. [PDF]

Micromachines (Basel), 2023
An U, Yoon G, Go D, Park J, Kim D, Kim J, Lee JS.   +6 more
europepmc   +1 more source

A capacitorless 1T-DRAM technology using gate-induced drain-leakage (GIDL) current for low-power and high-speed embedded memory

A capacitorless 1T-DRAM technology using gate-induced drain-leakage (GIDL) current for low-power and high-speed embedded memory
application/pdf 学術論文 (Article) 294853 ...
openaire   +1 more source

SRAM Cell Design Challenges in Modern Deep Sub-Micron Technologies: An Overview. [PDF]

Micromachines (Basel), 2022
Gul W, Shams M, Al-Khalili D.
europepmc   +1 more source

New observation and improvement in GIDL current of N-MOSFET's with various kinds of gate oxides under hot-carrier stress

, 1997
Degradation in gate-induced drain leakage (GIDL) current of n-MOSFET's with conventional SiO2 and oxynitride as gate dielectrics under hot-carrier stresses at different gate voltages is investigated.
Lai, PT, Zeng, X, Cheng, YC, Jingping, Xu   +3 more
core  

Performance analysis of electrostatic and transport characteristics of underlap-engineered gate-all-around carbon nanotube (CNT) FETs for nanoelectronics circuitry applications. [PDF]

Sci Rep
Bose SJ, Dhar RS, Hussein MI, Awwad F.
europepmc   +1 more source

Optimization of Structure and Electrical Characteristics for Four-Layer Vertically-Stacked Horizontal Gate-All-Around Si Nanosheets Devices. [PDF]

Nanomaterials (Basel), 2021
Zhang Q, Gu J, Xu R, Cao L, Li J, Wu Z, Wang G, Yao J, Zhang Z, Xiang J, He X, Kong Z, Yang H, Tian J, Xu G, Mao S, Radamson HH, Yin H, Luo J.   +18 more
europepmc   +1 more source

Remote Plasma Selective Silicon Etching Enabled Tunable Sub-Fin Process for Improved Parasitic Bottom Channel Control in Gate-All-Around Nanosheet Field-Effect Transistors. [PDF]

Nanomaterials (Basel)
Li J, Gao Y, Zhang DW.
europepmc   +1 more source

3-Levels Vertically Stacked Si Nanosheet GAA pFETs with Low-Temperature Interface Treatment for Cryogenic Application. [PDF]

Nanomaterials (Basel)
Qian L, Liu T, Liao M, Guo X, Xu S, Xu M, Zhang DW.   +6 more
europepmc   +1 more source

Enhancement-Mode InAlN/GaN MISHEMT with Low Gate Leakage Current

, 2012
We report an enhancement-mode InAlN/GaN MISHEMT with a low gate leakage current by a thermal oxidation technique under gate.The off-state source-drain current density is as low as～10~(17) A/mm at V_(GS)= 0 V and V_(DS) = 5 V.The threshold voltage is ...
Gu GD(顾国栋), Cai Y(蔡勇), Feng ZH(冯志红), Zhang BS(张宝顺), Liu B(刘波), Yu GH(于国浩), Dong ZH(董志华), Ceng CH(曾春红)   +7 more
core  

Repurposing Si CMOS nonidealities for stochastic and analog image processing. [PDF]

Sci Adv
Kwak B, Koo RH, Han C, Shin Y, Choi J, Kim D, Lee J, Im J, Cho Y, Lee JH, Shin W, Kwon D.   +11 more
europepmc   +1 more source