Results 51 to 60 of about 3,848,811 (155)
Small Structures, Volume 6, Issue 5, May 2025.A hybrid structure with heterostacked poly‐Si and In–Ga–O (IGO) is used as the channel layer of 3D NAND flash memory. IGO is used as the main channel to improve electrical properties and deviations while achieving high thermal stability. Poly‐Si is used to generate gate‐induced drain leakage current via band‐to‐band tunneling and thus enable the erase ...
Su‐Hwan Choi +15 more
wiley +1 more source
Controlling L-BTBT in Emerging Nanotube FETs Using Dual-Material Gate
IEEE Journal of the Electron Devices Society, 2018 Nanotube (NT) FETs have been proposed as the most promising architecture for the ultimate scaling of FETs. However, an enhanced L-BTBT restricts their scaling.
Aakash Kumar Jain +2 more
doaj +1 more source
Enhancing Device Performance with High Electron Mobility GeSn Materials
Advanced Electronic Materials, Volume 11, Issue 5, April 2025.Vertical gate‐all‐around nanowire n‐FETs based on GeSn‐alloys with Sn‐contents of 8% and 11% are presented. A great improvement in Ion, gm, and SS is found with increased Sn‐content. A fivefold increase in on‐current is observed for 11%‐GeSn compared to Ge, underlining the potential of GeSn for nanoelectronics applications.
Yannik Junk +10 more
wiley +1 more source
Nonlinear Variation Decomposition of Neural Networks for Holistic Semiconductor Process Monitoring
Advanced Intelligent Systems, Volume 6, Issue 10, October 2024.The nonlinear variation decomposition is proposed to decompose output variations from neural network inputs and to evaluate the influence of unit processes in each sample from semiconductor manufacturing. Herein, industrial 1Y nm node dynamic random‐access memory test vehicles with baseline and split tests introducing high‐k metal gates with a minimum ...
Hyeok Yun +11 more
wiley +1 more source
Lateral Migration‐based Flash‐like Synaptic Device for Hybrid Off‐chip/On‐chip Training
Advanced Electronic Materials, Volume 10, Issue 4, April 2024.The first‐ever engineering application of lateral migration in charge trap memory, which is perceived as a disadvantage in the memory industry, is proposed to achieve low‐power operation while maintaining superior retention and improving endurance. By varying the length of tunneling oxide, the proposed device diverges from conventional techniques in ...
Min‐Kyu Park +6 more
wiley +1 more source
Impact of Work-Function Variation in Ferroelectric Field-Effect Transistor
IEEE Journal of the Electron Devices SocietyWe analyzed the impact of work-function variation (WFV) in ferroelectric field-effect transistor (FeFET). To analyze the operation characteristics, we employed the technology computer-aided design (TCAD) simulations. After evaluating ferroelectricity (FE)
Su Yeon Jung +3 more
doaj +1 more source
The Effect of Gate-Induced Drain Leakage (GIDL) on Scaled MOSFETS of Low Power Consumptions [PDF]
, 2017 This project is aimed to study the impact of GateInduced Drain Leakage (GIDL) on scaled Metal-OxideSemiconductor Field-Effect Transistor (MOSFET) for low power efficient application. The MOSFET is operated with low power consumption. Microchip industries
Hassan, Nornikman; Faculty of Electronics and Computer Engineering (FKEKK), Universiti Teknikal Malaysia Melaka, Hang Tuah Jaya, 76100 Durian Tunggal, Melaka, Malaysia. +4 more
core
Time dependent dielectric breakdown and stress induced leakage current characteristics of 8Å EOT HfO2 N-MOSFETS [PDF]
, 2010 In this work we present the time dependent dielectric breakdown (TDDB) characteristics of LaO capped HfO2 layers with an equivalent oxide thickness of 8Å. The layers show maximum operating voltages in excess of 1V. Such high reliability can be attributed
Ragnarsson, Lars-Ake +8 more
core +2 more sources
Comprehensive Hammering and Parasitic BJT Effects in Vertically Stacked DRAM
IEEE AccessThis study investigates the row hammer tolerance and potential degradation by capacitive crosstalk (CC) and parasitic bipolar junction transistor (BJT) effect in vertically stacked dynamic random-access memory (VS-DRAM) using technology computer-aided ...
Minki Suh +7 more
doaj +1 more source
SiGe-Surrounded Bitline Structure for Enhancing 3D NAND Flash Erase Speed
Applied SciencesThree-dimensional NAND Flash has adopted the cell-over-peripheral (COP) structure to increase storage density. Unlike the conventional structure, the COP structure cannot directly increase the channel potential via substrate bias during the erase ...
Dohyun Kim, Wonbo Shim
doaj +1 more source