Controlling L-BTBT in Emerging Nanotube FETs Using Dual-Material Gate
Nanotube (NT) FETs have been proposed as the most promising architecture for the ultimate scaling of FETs. However, an enhanced L-BTBT restricts their scaling.
Aakash Kumar Jain +2 more
doaj +1 more source
Enhancing Device Performance with High Electron Mobility GeSn Materials
Vertical gate‐all‐around nanowire n‐FETs based on GeSn‐alloys with Sn‐contents of 8% and 11% are presented. A great improvement in Ion, gm, and SS is found with increased Sn‐content. A fivefold increase in on‐current is observed for 11%‐GeSn compared to Ge, underlining the potential of GeSn for nanoelectronics applications.
Yannik Junk +10 more
wiley +1 more source
Nonlinear Variation Decomposition of Neural Networks for Holistic Semiconductor Process Monitoring
The nonlinear variation decomposition is proposed to decompose output variations from neural network inputs and to evaluate the influence of unit processes in each sample from semiconductor manufacturing. Herein, industrial 1Y nm node dynamic random‐access memory test vehicles with baseline and split tests introducing high‐k metal gates with a minimum ...
Hyeok Yun +11 more
wiley +1 more source
Lateral Migration‐based Flash‐like Synaptic Device for Hybrid Off‐chip/On‐chip Training
The first‐ever engineering application of lateral migration in charge trap memory, which is perceived as a disadvantage in the memory industry, is proposed to achieve low‐power operation while maintaining superior retention and improving endurance. By varying the length of tunneling oxide, the proposed device diverges from conventional techniques in ...
Min‐Kyu Park +6 more
wiley +1 more source
Impact of Work-Function Variation in Ferroelectric Field-Effect Transistor
We analyzed the impact of work-function variation (WFV) in ferroelectric field-effect transistor (FeFET). To analyze the operation characteristics, we employed the technology computer-aided design (TCAD) simulations. After evaluating ferroelectricity (FE)
Su Yeon Jung +3 more
doaj +1 more source
Comprehensive Hammering and Parasitic BJT Effects in Vertically Stacked DRAM
This study investigates the row hammer tolerance and potential degradation by capacitive crosstalk (CC) and parasitic bipolar junction transistor (BJT) effect in vertically stacked dynamic random-access memory (VS-DRAM) using technology computer-aided ...
Minki Suh +7 more
doaj +1 more source
Mechanism analysis of gate-induced drain leakage in off-state n-MOSFET
An analytical expression for both band-to-band and band-trap-band indirect tunnelings is used to study the gate-induced drain leakage (GIDL) current of MOSFETs measured before and after hot-carrier stress.
J.P. Xu +7 more
core +1 more source
SiGe-Surrounded Bitline Structure for Enhancing 3D NAND Flash Erase Speed
Three-dimensional NAND Flash has adopted the cell-over-peripheral (COP) structure to increase storage density. Unlike the conventional structure, the COP structure cannot directly increase the channel potential via substrate bias during the erase ...
Dohyun Kim, Wonbo Shim
doaj +1 more source
Analysis of Random Telegraph Noise after Soft Breakdown in the Gate Induced Drain Leakage Current [PDF]
학위논문 (석사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2013. 8. 신형철.A Random Telegraph Noise (RTN) in leakage current has been important for discovering the cause of Variable Retention Time (VRT) in Dynamic Random Access Memory (DRAM) cell transistor.
이슬기
core
Enhanced off-state leakage currents in n-channel MOSFET's with N2O-grown gate dielectric [PDF]
This paper reports on the off-state drain (GIDL) and gate current (Ig) characteristics of n-channel MOSFETs using thin thermal oxide (OX), N2O-nitrided oxide (N2ON), and N2O-grown oxide (N20G) as gate dielectrics.
Ng, WT, Xu, Z, Lai, PT
core +1 more source

