Results 151 to 160 of about 1,624 (169)

FinFET Source/Drain Profile Optimization Considering GIDL for Low Power Applications

2005 International Conference On Simulation of Semiconductor Processes and Devices, 2005
We have investigated sub-50nm FinFET design to be used in low power applications, through 3D device simulations considering gate-induced drain leakage (GEDL). It is found that the body-tied structure is necessary for dopedchannel FinFET to reduce off-state current (I off ).
K. Tanaka, K. Takeuchi, M. Hane
openaire   +1 more source

Approximations to field-effect factor and their use in GIDL modeling

18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA), 2011
New analytical approximations to field-effect factor used in gate induced drain leakage (GIDL) current modeling are presented. Modeling results for GIDL currents in sphere-shaped recessed channel array transistor (SRCAT) and NMOSFET obtained with the use of new approximations were compared to the measurement data in order to prove the validity of the ...
Nikita Kozhukhov, null Byoungchan Oh, null Hyungcheol Shin   +2 more
openaire   +1 more source

MOSFET GIDL Current Variation with Impurity Doping Concentration – A Novel Approach

2019 International Conference on Power Electronics, Control and Automation (ICPECA), 2019
This paper depicts the actual variation of gate-induced-drain-leakage current with impurity doping concentration by complete qualitative and quantitative approach. De Casteljau’s algorithm is applied to describe the band-to-band tunneling in a thin gate oxide n-MOSFET and the results are remarkably matched.
Arnesh Sen, Aishik Das, Jayoti Das
openaire   +1 more source

Degradation of ultra-thin gate oxide LDD NMOSFET under GIDL stress

Journal of Semiconductors, 2009
The degradation of device under GIDL (gate-induced drain leakage current) stress has been studied using LDD NMOSFETs with 1.4 nm gate oxides. Experimental result shows that the degradation of device parameters depends more strongly on Vd than on Vg. The characteristics of the GIDL current are used to analyze the damage generated during the stress.
Hu Shigang, Hao Yue, Cao Yanrong, Ma Xiaohua, Wu Xiaofeng, Chen Chi, Zhou Qingjun   +6 more
openaire   +1 more source

Gate-induced drain leakage (GIDL) in MFMIS and MFIS negative capacitance FinFETs

Current Applied Physics, 2020
Abstract The gate induced drain leakage (GIDL) effect in negative capacitance (NC) FinFET is investigated. A Landau–Ginzburg–Devonshire equation (which considers the polarization gradient in ferroelectric material) is used to estimate the characteristics of the NC FinFET.
Jinhong Min, Gihun Choe, Changhwan Shin
openaire   +1 more source

Enhanced endurance of dual-bit SONOS NVM cells using the GIDL read method

2008 Symposium on VLSI Technology, 2008
Gate-induced drain leakage (GIDL) current is demonstrated to be more sensitive to charge stored locally within the gate-dielectric stack, as compared with the transistor threshold voltage (VT). Thus the sensing of GIDL rather than VT is advantageous for dual-bit SONOS NVM cell read operation, not only because it mitigates the complementary-bit disturb (
Alvaro Padilla, null Sunyeong Lee, David Carlton, null Tsu-Jae King Liu   +3 more
openaire   +1 more source

Investigation of GIDL current Injection Disturb Mechanism in two-transistor-eNVM memory devices

2008 IEEE International Integrated Reliability Workshop Final Report, 2008
A programming disturb mechanism in the uniform channel program and erase (UCPE) eFlash 2TC (two transistor cell) is investigated. High GIDL current from the SG (selected gate) on the selected row and unselected columns introduce additional gate disturbs in a high density eFlash product. It is observed that the 1TC eFlash without an SG configuration did
S.R. Kim, K. J. Han, Junmin Lee, Tony Zhou, K.S. Lee, Patty Liu, P.Y. Lee, Huan-Chung Tseng, Brian Cronquist   +8 more
openaire   +1 more source

Compact modeling of GIDL-assisted erase in 3-D NAND Flash strings

Journal of Computational Electronics, 2019
This paper presents a physics-based compact model able to describe the time dynamics of the erase operation in three-dimensional NAND Flash strings exploiting gate-induced drain leakage at the selector to increase the string potential. The model accurately reproduces all the main phases of the erase operation and allows to calculate the threshold ...
G. Malavena, A. Mannara, A. L. Lacaita, A. Sottocornola Spinelli, C. Monzio Compagnoni   +4 more
openaire   +1 more source

Improved extraction of GIDL in FDSOI devices for proper junction quality analysis

2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2011
In this work, an optimized method to extract GIDL parameters has been used to characterize junction quality in FDSOI devices. This paper gives a practical methodology to properly apply this method: first, it insists on the importance to discriminate the respective contributions of GIDL and gate tunneling in drain current.
Xu, C., Batude, P., Romanjek, K., Le Royer, C., Tabone, C., Previtali, B., Jaud, M-A., Garros, X., Vinet, M., Poiroux, T., Rafhay, Quentin, Mouis, M.   +11 more
openaire   +2 more sources

Compact Model for Trap Assisted Tunneling based GIDL

2022 Device Research Conference (DRC), 2022
Chetan Kumar Dabhi, Girish Pahwa, Sayeef Salahuddin, Chenming Hu   +3 more
openaire   +1 more source