Results 11 to 20 of about 36,186 (209)

Selective harmonic elimination pulse width modulation based hybrid multilevel inverter topology with reduced components

IET Power Electronics, EarlyView., 2022
Abstract In this paper, a reduced switch count single‐phase hybrid multilevel inverter (MLI) is presented. Level generation unit (LGU) and polarity changing unit (PCU) are the two parts of the presented topology which are connected in series. Other advantages of the proposed topology include the reduced switch count, higher level generation with ...
Mohammad Wasiq, Mudasir Ahmed Memon, Prashant Shrivastava, Saad Mekhilef, Mehdi Seyedmahmoudian, Alex Stojcevski, Ben Horan   +6 more
wiley   +1 more source

Power quality enhancement in asymmetrical cascaded multilevel inverter using modified carrier level shifted pulse width modulation approach

IET Power Electronics, EarlyView., 2022
New modified carrier‐based level shifted pulse width modulation approaches for single‐phase trinary dc source fed cascaded H‐bridge inverters are proposed in this article. In order to suppress the lower order harmonics, the carrier frequency is often tuned higher. However, switching and electromagnetic interference problems have a significant influence
Arun Vijayakumar, Albert Alexander Stonier, Geno Peter, Ashok Kumar Loganathan, Vivekananda Ganji   +4 more
wiley   +1 more source

A new symmetric modular eleven‐level inverter using single and double source unit for low voltage applications with reduced number of switches

IET Power Electronics, EarlyView., 2023
This study introduces a new modular multilevel inverter that can produce five levels of positive voltage using only six power switches and five DC voltage sources. The basic unit is composed of a single‐ and double‐source (SDS) unit. SDS reduces the number of power electronic components, such as the insulated gate bipolar transistors, freewheeling ...
Naser Fakhri, Sara Laali, Mohammad Salay Naderi, Hossein Rahimi, Saeid Gholami Farkoush   +4 more
wiley   +1 more source

A nine‐level T‐type inverter (9L‐TTI) with voltage boost capability

IET Power Electronics, EarlyView., 2023
A new multi‐level inverter topology with boosting feature considering the reduced switch count has been presented, compared and validated. Abstract This paper introduces a 9L T‐type boost inverter (9L‐TTI) based multilevel topology, which generates a nine‐level output voltage in the boost mode.
Zarren Firdous, Saad Mekhilef, Nidhi Mishra, Asif Mustafa, Mehdi Seyedmahmoudian, Alex Stojcevski   +5 more
wiley   +1 more source

Dual source novel nine level inverter (DSN2LI) design with minimum active devices and inherent polarity generation

IET Power Electronics, EarlyView., 2023
This article presents a dual‐source novel nine‐level inverter (DSN2LI) featuring minimal devices. Utilizing eight switches, which include 2 bidirectional switching devices and 2 uneven dc links, the proposed DSN2LI generates nine levels. The DSN2LI employs the utilization of trinary geometric DC links.
Arun Vijayakumar, Albert Alexander Stonier, Geno Peter, Vivekananda Ganji   +3 more
wiley   +1 more source

Machine learning based model predictive control for grid connected enhanced switched capacitor cross‐connected switched multi‐level inverter (ESC3SMLI)

IET Power Electronics, EarlyView., 2023
This article describes an enhanced switched capacitor cross‐connected switched multilevel inverter (ESC3SMLI) with machine learning‐based model‐predictive control (ML‐MPCM). An improved switched capacitor cross connected switched multilevel inverter featuring minimal devices are presented. The proposed ESC3SMLI produces nine levels using eight switches,
Arun Vijayakumar, Albert Alexander Stonier, Geno Peter, Ezhil Vignesh, Vivekananda Ganji   +4 more
wiley   +1 more source

A three‐phase three‐level converter with shared flying capacitors

IET Power Electronics, EarlyView., 2023
Three‐phase multilevel converters use a high number of components which increases their size. As specific weight reduction is a work of interest for embedded system applications, this paper presents a topology aiming to optimize volume and mass for a three‐level three‐phase inverter. The number of passive and active components is reduced thanks to the ‘
Maxime Pain, Guillaume Gateau, Jean‐Marc Blaquiere   +2 more
wiley   +1 more source

Triple boost switched capacitor multilevel inverter (TB‐SCMLI) with reduced components and self‐voltage balance

IET Power Electronics, EarlyView., 2023
The proposed TB‐SCMLI is able to provide seven levels of output voltage by balancing the voltage of two capacitors with the given control logic. The various SCMLIs are evaluated to determine the contribution of the suggested TB‐SCMLI topology's merits and downsides.
Md. Reyaz Hussan, Mohammed A. Al‐Hitmi, Marif Daula Siddique, Shirazul Islam, Atif Iqbal   +4 more
wiley   +1 more source

An assessment of H‐bridge less grid‐tied multilevel inverter with minimum device count and lesser total standing voltage

IET Power Electronics, EarlyView., 2023
An innovative switched‐capacitor‐based inverter is proposed in this article. The suggested converter can produce a five‐level output voltage by utilizing minimal components (single dc source, six switches, and one capacitor). The effectiveness of the suggested inverter is verified by experimental results using hardware in loop OPAL‐RT OP4510.
Tamiru Debela, Jiwanjot Singh, Vijay K. Sood   +2 more
wiley   +1 more source

Harmonic elimination of a fifteen‐level inverter with reduced number of switches using genetic algorithm

IET Power Electronics, EarlyView., 2023
This article presents a Fifteen‐level inverter topology that has a lesser number of switches (12) and can accommodate isolated DC sources. The total harmonic elimination (THD) of the proposed topology using genetic algorithm is within the IEEE 519 standards. Further, the fifteen‐level inverter is implemented in Hardware and firing pulses were generated
Yogesh Joshi, Shimi Sudha Letha, Farhad Ilahi Bakhsh, Gopal Lal Jaat, Suyash Tilak   +4 more
wiley   +1 more source