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Inverse lithography technology at low k1: placement and accuracy of assist features
SPIE Proceedings, 2006An implementation of inverse lithography technology is studied with special attention to illustrating and analyzing the placement, accuracy, and efficacy of subresolution assist elements. One-dimensional placement through pitch is characterized, and 2D capability is demonstrated for repeated patterns.
Linyong Pang
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Considering MEEF in inverse lithography technology (ILT) and source mask optimization (SMO)
Proceedings of SPIE, 2008Mask Error Enhancement Factor (MEEF) plays an increasingly important role in the DFM and RET flow required to continue shrinking designs in the low-k1 lithography regime. The ability to model and minimize MEEF during lithography optimization and RET application is essential to obtain a usable process window (PW).
Thuc Dam, Peter Hu, Bob Gleason
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A Gradient-Based Inverse Lithography Technology for Double-Dipole Lithography
2009 International Conference on Simulation of Semiconductor Processes and Devices, 2009Resolution enhancement techniques (RETs) have become indispensable for the sub-wavelength optical lithography. Inverse lithography technology (ILT) is one kind of RETs, which attempts to consider the mask synthesis as an inverse problem and compute the optimum mask by using the entire area of the design pattern with a rigorous mathematical approach ...
Wei Xiong +4 more
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Fast inverse lithography technology
SPIE Proceedings, 2006Many RET technologies, such as rule and model based OPC, the use of sub-resolution assist features, and various PSM methodologies, can be thought of as heuristics employed in an attempt to design improved photomasks. Unfortunately, these traditional approaches are running into severe difficulties at advanced technology nodes (90nm and beyond).
Daniel S. Abrams, Linyong Pang
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Block-based inverse lithography technology with adaptive level-set algorithm
Optics and Laser TechnologyGonzalo R. Arce, Shengen Zhang, Xu Ma
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ECS Transactions, 2010
For semiconductor manufacturers moving toward advanced technology nodes -32nm, 22nm and below - lithography presents the greatest challenge, because it is fundamentally constrained by basic principles of optical physics. Because no major lithography hardware improvements are expected over the next couple years, Computational Lithography has been ...
Linyong Pang +10 more
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For semiconductor manufacturers moving toward advanced technology nodes -32nm, 22nm and below - lithography presents the greatest challenge, because it is fundamentally constrained by basic principles of optical physics. Because no major lithography hardware improvements are expected over the next couple years, Computational Lithography has been ...
Linyong Pang +10 more
openaire +1 more source
Inverse lithography technology at chip scale
SPIE Proceedings, 2006In this paper we describe, from the user's point of view, how Inverse Lithography Technology (ILT) differs from Optical Proximity Correction (OPC). We discuss some specifics of ILT at chip-scale. We show simulation and experimental results from 90nm and 65nm semiconductor nodes, comparing results from ILT-generated masks and OPC-generated masks for ...
Benjamin Lin +10 more
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Hot-Spots Aware Inverse Lithography Technology
ECS Transactions, 2009This paper presents a new method of Inverse Lithography Technology (ILT) to accelerate its optimization process and convergence, which involves two steps in iteration: the first step is to find hot-spots in the layout in the optimization process and the second step is to optimize on the hot-spot areas.
Yiwei Yang +3 more
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GMUNet-ILT: A lightweight MLP-based network for Inverse Lithography Technology
2025 International Symposium of Electronics Design Automation (ISEDA)Dawei Gao, Yongyu Wu, Zebang Lin
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