Results 171 to 180 of about 3,871 (202)

Pushing the lithography limit: applying inverse lithography technology (ILT) at the 65nm generation

SPIE Proceedings, 2006
This paper presents the results of applying ILT to SMIC's first 65nm tape out. ILT mathematically determines the mask features that produce the desired on-wafer results for best pattern fidelity, largest process window or an desired combination of both.
Chi-Yuan Hung, Bin Zhang, Eric Guo, Linyong Pang, Yong Liu, Kechang Wang, Grace Dai   +6 more
openaire   +1 more source

Inverse lithography technology: verification of SRAM cell pattern

SPIE Proceedings, 2005
Inverse Lithography Technology (ILT), a mask creation technique with a decades-long history, has the potential for improving pattern fidelity and lithographic process window for features in dense memory ce lls (such as SRAM) for 100nm and 65nm nodes and beyond. Currently, the quality of OPC/RET/DfM/DfY methodology is verified based on CD measurements.
Artur Balasinski, Andrew Moore, Nader Shamma, Timothy Lin, Hee-hong Yang   +4 more
openaire   +1 more source

Seamless-merging-oriented parallel inverse lithography technology

Journal of Semiconductors, 2009
Inverse lithography technology (ILT), a promising resolution enhancement technology (RET) used in next generations of IC manufacture, has the capability to push lithography to its limit. However, the existing methods of ILT are either time-consuming due to the large layout in a single process, or not accurate enough due to simply block merging in the ...
Yang Yiwei, Shi Zheng, Shen Shanhu
openaire   +1 more source

A new algorithm of inverse lithography technology for mask complexity reduction

Journal of Semiconductors, 2012
A new complexity penalty term called the global wavelet penalty is introduced, which evaluates the high-frequency components of masks more profoundly by applying four distinctive Haar wavelet transforms and choosing the optimal direction on which the highest frequency components of the mask will be removed.
Yanghuan Li, Zheng Shi, Zhen Geng, Yiwei Yang, Xiaolang Yan   +4 more
openaire   +1 more source

Manufacturability study of masks created by inverse lithography technology (ILT)

SPIE Proceedings, 2005
As photolithography is pushed to fabricate deep-sub wavelength devices for 90nm, 65nm and smaller technology nodes using available exposure tools (i.e., 248nm, 193nm steppers), photomask capability is becoming extremely critical. For example, PSM masks require more complicated processing; aggressive OPC makes the writing time longer and sometimes ...
Patrick M. Martin, C. J. Progler, G. Xiao, R. Gray, L. Pang, Y. Liu   +5 more
openaire   +1 more source

SRAF rule extraction and insertion based on inverse lithography technology

Optical Microlithography XXXII, 2019
The placement and size of SRAF (sub-resolution assisted feature) can greatly affect the overlapped process window. The time-consuming inverse lithography technology (ILT) can provide the co-optimization for both main pattern and SRAFs, which can guarantee the results with high precision.
Xiaojing Su, Pengzheng Gao, Yayi Wei, Weijie Shi   +3 more
openaire   +1 more source

A Mask Generation Approach to Double Patterning Technology with Inverse Lithography

Japanese Journal of Applied Physics, 2008
Pattern reduction has generated much interest in developing effective methods of reducing the feature sizes of microelectronic and data-storage devices. For below-32-nm node technology, the bottom-up approach, namely, self-assembly, has obstacles such as the insufficient support of processes and mass production, and the top-down approaches, namely ...
Sang-Kon Kim, Hye-Keun Oh, Young-Dae Jung, Ilsin An   +3 more
openaire   +1 more source

Evaluation of inverse lithography technology for 55nm-node memory device

SPIE Proceedings, 2008
Model based OPC has been generally used to correct proximity effects down to ~50 nm critical dimensions at k1 values around 0.3. As design rules shrink and k1 drops below 0.3, however; it is very hard to obtain enough process window and acceptable MEEF (Mask Error Enhancement Factor) with conventional model based OPC.
Byung-ug Cho, Sung-woo Ko, Jae-seung Choi, Cheol-Kyun Kim, Hyun-jo Yang, DongGyu Yim, David Kim, Bob Gleason, KiHo Baik, Ying Cui, Thuc Dam, Linyong Pang   +11 more
openaire   +1 more source

Improvement of KrF contact layer by inverse lithography technology with assist feature

SPIE Proceedings, 2010
Patterning of contact holes using KrF lithography system is one of the most challenging tasks for the sub-90nm technology node,. Contact hole patterns can be printed with a KrF lithography system using Off-Axis Illumination (OAI) such as Quasar or Quadrupole.
Sungho Jun, Yeon-Ah Shim, Jaeyoung Choi, Kwangsun Choi, Jae-won Han, Kechang Wang, John McCarthy, Guangming Xiao, Grace Dai, DongHwan Son, Xin Zhou, Tom Cecil, David Kim, KiHo Baik   +13 more
openaire   +1 more source

Laser and e-beam mask-to-silicon with inverse lithography technology (ILT)

SPIE Proceedings, 2005
This paper presents ILT masks written by a DUV laser writer and a VSB e-beam writer, and their corresponding wafer print results. ILT mathematically determine the mask features that produce the desired on-wafer results. ILT-generated masks sometimes are non-intuitive, and different than those produced by past approaches; therefore, their ...
Linyong Pang, Nader Shamma, Paul Rissman, Dan Abrams   +3 more
openaire   +1 more source