Results 21 to 30 of about 481,437 (293)

Methods of Improving Time Efficiency of Decomposition Dedicated at FPGA Structures and Using BDD in the Process of Cyber-Physical Synthesis

open access: yesIEEE Access, 2019
Physical systems may be carried out in both hardware and software. Hardware is based on implementing appropriate logic functions in FPGA structures connected with a physical layer of cyber-physical systems (CPSs).
Adam Opara, Marcin Kubica, Dariusz Kania
doaj   +1 more source

Dual Logic Area Optimization of Finite State Machine [PDF]

open access: yesJisuanji gongcheng, 2016
To cope with the problem that exists in the area optimization of Finite State Machine(FSM) by only using Traditional Boolean (TB) logic,a novel algorithm for FSM area optimization using both traditional Boolean logic and Reed-Muller (RM) logic,namely ...
LIN Weijian,WANG Lunyao,XIA Yinshui
doaj   +1 more source

LOT: Logic Optimization with Testability - new transformations for logic synthesis [PDF]

open access: yes, 1998
A new approach to optimize multilevel logic circuits is introduced. Given a multilevel circuit, the synthesis method optimizes its area while simultaneously enhancing its random pattern testability.
Chatterjee, Mitrajit   +2 more
core   +2 more sources

Using Program Synthesis for Program Analysis [PDF]

open access: yes, 2015
In this paper, we identify a fragment of second-order logic with restricted quantification that is expressive enough to capture numerous static analysis problems (e.g.
David, Cristina   +2 more
core   +4 more sources

Secure Logic Synthesis

open access: yes, 2004
This paper describes the synthesis of dynamic differential logic to increase the resistance of FPGAs against Differential Power Analysis. Compared with an existing technique, it saves more than a factor 2 in slice utilization. Experimental results indicate that a secure version of the AES algorithm can now be implemented with a mere doubling of the ...
Tiri, K., Verbauwhede, Ingrid
openaire   +2 more sources

Work in progress: introduction of K-map based nano-logic synthesis as knowledge module in logic design course [PDF]

open access: yes, 2007
This work in progress reports an effort of introducing knowledge module regarding novel nano-devices and novel logic primitives in undergraduate logic design class.
Bhanja, S., Srivastava, S.
core   +1 more source

Fast and Reconfigurable Logic Synthesis in Memristor Crossbar Array

open access: yesAdvanced Intelligent Systems, 2022
Memristor is a potential basic unit for the in‐memory computing system, which is an approach to break the memory wall of the traditional computer. However, low switching speed, nonuniform device characteristics, and inefficient logic synthesis hinder the
Wei Wang   +11 more
doaj   +1 more source

Algorithms for extracting subsystems from a multilevel representation of a system of Boolean functions for joint minimization

open access: yesInformatika
Objectives. The purpose of experimental research is to determine the effectiveness of new algorithms for extracting the so-called connected subsystems from formula descriptions of the original system of Boolean functions.
P. N. Bibilo   +2 more
doaj   +1 more source

Advanced Datapath Synthesis using Graph Isomorphism

open access: yes, 2017
This paper presents an advanced DAG-based algorithm for datapath synthesis that targets area minimization using logic-level resource sharing. The problem of identifying common specification logic is formulated using unweighted graph isomorphism problem ...
Choudhury, Mihir   +3 more
core   +1 more source

Synthesis and Optimization of Reversible Circuits - A Survey

open access: yes, 2013
Reversible logic circuits have been historically motivated by theoretical research in low-power electronics as well as practical improvement of bit-manipulation transforms in cryptography and computer graphics.
Arabzadeh M.   +32 more
core   +1 more source

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