Results 41 to 50 of about 49,624 (163)

A High-Level LTL Synthesis Format: TLSF v1.1 [PDF]

open access: yesElectronic Proceedings in Theoretical Computer Science, 2016
We present the Temporal Logic Synthesis Format (TLSF), a high-level format to describe synthesis problems via Linear Temporal Logic (LTL). The format builds upon standard LTL, but additionally allows to use high-level constructs, such as sets and ...
Swen Jacobs   +2 more
doaj   +1 more source

Real-Time Model-Checking: Parameters everywhere [PDF]

open access: yesLogical Methods in Computer Science, 2007
In this paper, we study the model-checking and parameter synthesis problems of the logic TCTL over discrete-timed automata where parameters are allowed both in the model (timed automaton) and in the property (temporal formula). Our results are as follows.
Veronique Bruyere, Jean-Francois Raskin
doaj   +1 more source

A Novel QCA Design of Energy-Efficient Three-Input AND/OR Circuit

open access: yesQuantum Reports
One of the nanoscale technologies that shows its capability of implementing integrated digital circuits with low power, high speed, and high density is quantum-dot cellular automata (QCA). The fundamental device for designing and implementing circuits in
Amjad Almatrood
doaj   +1 more source

Binary decision diagram‐based synthesis technique for improved mapping of Boolean functions inside memristive crossbar‐slices

open access: yesIET Computers & Digital Techniques, 2021
Memristors are two‐terminal nano‐electronic devices that make it possible to design non‐volatile memory and logic circuits with high integration density.
Anindita Chakraborty   +5 more
doaj   +1 more source

Approximate Logic Synthesis by Symmetrization [PDF]

open access: yes2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2019
Approximate synthesis is a recent trend in logic synthesis that changes some outputs of a logic specification to take advantage of error tolerance of some applications and reduce complexity and consumption of the final implementation. We propose a new approach to approximate synthesis of combinational logic where we derive its closest symmetric ...
Anna Bernasconi   +2 more
openaire   +2 more sources

A Technology Mapping of FSMs Based on a Graph of Excitations and Outputs

open access: yesIEEE Access, 2019
A logic synthesis for finite-state machines (FSMs) aimed at programmable array logic (PAL)-based complex programmable logic devices is proposed here. This approach consists of the simultaneous synthesis of a transition function and an output function ...
Marcin Kubica   +2 more
doaj   +1 more source

Technology independent optimization when implementing sparse systems of disjunctive normal forms of Boolean functions in ASIC

open access: yesInformatika
Objectives. The problem of choosing the best methods and programs for circuit implementation as part of digital ASIC (Application-Specific Integrated Circuit) sparse systems of disjunctive normal forms (DNF) of completely defined Boolean functions is ...
P. N. Bibilo, S. N. Kardash
doaj   +1 more source

Area–Oriented Technology Mapping for LUT–Based Logic Blocks

open access: yesInternational Journal of Applied Mathematics and Computer Science, 2017
One of the main aspects of logic synthesis dedicated to FPGA is the problem of technology mapping, which is directly associated with the logic decomposition technique.
Kubica Marcin, Kania Dariusz
doaj   +1 more source

Function Synthesis Algorithm of RTD-Based Universal Threshold Logic Gate

open access: yesJournal of Applied Mathematics, 2015
The resonant tunneling device (RTD) has attracted much attention because of its unique negative differential resistance characteristic and its functional versatility and is more suitable for implementing the threshold logic gate. The universal logic gate
Maoqun Yao   +3 more
doaj   +1 more source

BDD-Based Topology Optimization for Low-Power DTIG FinFET Circuits

open access: yesActive and Passive Electronic Components, 2019
This paper proposed a logic synthesis method based on binary decision diagram (BDD) representation. The proposed method is optimized for dual-threshold independent-gate (DTIG) FinFET circuits.
Haiyan Ni   +3 more
doaj   +1 more source

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