Results 11 to 20 of about 21,543 (210)

High mobility III-V MOSFETs for RF and digital applications [PDF]

, 2007
Developments over the last 15 years in the areas of materials and devices have finally delivered competitive III-V MOSFETs with high mobility channels. This paper briefly reviews the above developments, discusses properties of the GdGaO/Ga2O3 MOS systems,
Kalna, K., A. Zlotnicka, Moran, D.A.J., D. Macintyre, H. Zhou, O. Hartin, Asenov, A., Zlotnicka, A., Passlack, M., M. Tutt, X. Li, Y.-B. Park, K. Kalna, Droopad, R., Hartin, O., Fejes, P., J. Abrokwah, E. Johnson, Tutt, M., Abrokwah, J., S. Thoms, A. Asenov, Zurcher, P., Rajagopalan, K., Thoms, S., Park, Y-B, Macintyre, D., D.A.J. Moran, M. Passlack, K. Rajagopalan, Li, X., Thayne, I.G., Zhou, H., P. Fejes, P. Zurcher, I.G. Thayne, R. Droopad, Hill, R.J.W., R.J.W. Hill, Johnson, E.   +39 more
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Improved drive current in RF vertical MOSFETS using hydrogen anneal [PDF]

, 2011
This letter reports a study on the effect of a hydrogen anneal after silicon pillar etch of surround-gate vertical MOSFETs intended for RF applications.
Tan, L., Redman-White, W., Ashburn, P., Hall, S., M. M. A. Hakim, Abuelgasim, A., L. Tan, W. Redman-White, de Groot, C.H., C. H. de Groot, Hakim, M.M.A., A. Abuelgasim, S. Hall, P. Ashburn   +13 more
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Improved sub-threshold Slope in RF vertical MOSFETS using a frame gate architecture [PDF]

, 2008
We report a CMOS-compatible vertical MOSFET, which incorporates a frame gate architecture suitable for application in RF circuits. Fabricated surround gate vertical MOSFETs with the frame gate architecture show no degradation of short channel effects ...
Tan, L., Redman-White, W., Ashburn, P., W. R.- White, Buiu, O., Hall, S., M. M. A. Hakim, L. Tan, O. Buiu, Hakim, M.M.A., T. Uchino, S. Hall, Uchino, T., P. Ashburn   +13 more
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Improved sub-threshold slope in short channel vertical MOSFETs using FILOX oxidation [PDF]

, 2009
This paper investigates the origins of sub-threshold slope degradation in vertical MOSFETs (v-MOSFETs) due to dry etching of the polysilicon surround gate.
Tan, L., Redman-White, W., Ashburn, P, Buiu, O., Hall, S., Hakim, M M A   +5 more
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Single, double and surround gate vertical MOSFETs with reduced parasitic capacitance [PDF]

, 2004
The vertical MOSFET structure is one of the solutions for reducing the channel length of transistors under 50nm. Surround gates can be easily realised in vertical MOSFETs which offer increased channel width per unit silicon area.
Wang, Y, Hemment, P L F, E. Gili, Hall, S, D.C. Donaghy, Uchino, T, Donaghy, D C, V.D. Kunz, C.H. de Groot, P.L.F. Hemment, Ashburn, P, T. Uchino, S. Hall, Gili, E, de Groot, C H, Y. Wang, P. Ashburn, Kunz, V D   +17 more
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Linearity and mobility degradation in strained Si MOSFETs with thin gate dielectrics [PDF]

, 2010
As gate dielectrics are scaled to a few atomic layers and the channel doping is increased to mitigate short channel effects, high vertical electric fields cause considerable mobility degradation through surface-roughness scattering in silicon MOSFETs ...
O'Neill, Anthony G., Olsen, Sarah H., Anthony O’Neill, Olayiwola Alatise, Alatise, Olayiwola M., Sarah Olsen   +5 more
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Vertical MOSFETs for high performance, low cost CMOS [PDF]

, 2007
-We present a review of recent reports on vertical MOSFETs which includes a summary of our own research in this area. Such devices can offer a decananometer channel length in a relaxed lithography. Furthermore, the footprint is substantially smaller than
Tan, L., M.M. Hakim, Hakim, M. M. A., Ashburn, P., White, W. Redman-, Hall, S., Buiu, O., L. Tan, W. Redman-White, O. Buiu, S. Hall, T. Uchino, Uchino, T., P. Ashburn   +13 more
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180nm metal gate, high-k dielectric, implant-free III--V MOSFETs with transconductance of over 425 μS/μm [PDF]

, 2007
: Data is reported from 180 nm gate length GaAs n-MOSFETs with drive current (Ids,sat) of 386 μA/μm (Vg=Vd =1.5 V), extrinsic transconductance (gm) of 426 μS/μm, gate leakage ( jg,limit) of 44 nA/cm2, and on resistance (Ron) of 1640 Ω μm. The gm and Ron
Moran, D.A.J., Passlack, M., Li, X., Thoms, S., Thayne, I.G., Hill, R.J.W., Macintyre, D., Droopad, R., Zhou, H.   +8 more
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Effect of oxide interface roughness on the threshold voltage fluctuations in decanano MOSFETs with ultrathin gate oxides [PDF]

, 2000
In this paper we use the density gradient (DG) simulation approach to study, in 3D, the effect of local oxide thickness fluctuations on the threshold voltage of decanano MOSFETs on a statistical scale.
Kalna, K., Asenov, A.
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The impact of repetitive unclamped inductive switching on the electrical parameters of low-voltage trench power nMOSFETs [PDF]

, 2010
The impact of hot-carrier injection (HCI) due to repetitive unclamped inductive switching (UIS) on the electrical performance of low-voltage trench power n-type MOSFETs (nMOSFETs) is assessed.
Khan, Khalid Saeed, Jim Parkin, Parkin, Jim, George Petkos, Keith Heppenstall, Rutter, Philip, Ian Kennedy, Petkos, George, Adrian Koh, Heppenstall, Keith, Philip Rutter, Kennedy, Ian, Olayiwola Alatise, Khalid Khan, Alatise, Olayiwola M., Koh, Adrian   +15 more
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