Scaling study of Si and strained Si n-MOSFETs with different high-k gate stacks [PDF]
, 2004 Using ensemble Monte Carlo device simulations, this paper studies the impact of interface roughness and soft-optical phonon scattering on the performance of sub-100nm Si and strained Si MOSFETs with different high-k gate stacks. Devices with gate lengths
Watling, J. R. +9 more
core +1 more source
Modeling the impact of the trench depth on the gate-drain capacitance in power MOSFETs [PDF]
, 2011 Trench depth is important in low-voltage trench MOSFETs because it affects the switching losses through the gate-drain capacitance (C(GD)).
Ian Kennedy +11 more
core +1 more source
Improved analog performance in strained-Si MOSFETs using the thickness of the silicon-germanium strain-relaxed buffer as a design parameter [PDF]
, 2009 The impact of self-heating in strained-Si MOSFETs on the switching characteristics of a complementary-metal-oxide-semiconductor (CMOS) inverter and the voltage gain of a push-pull inverting amplifier is assessed by technology-computer-aided-design (TCAD)
O'Neill, Anthony G. +3 more
core +1 more source
Effects of neglecting carrier tunneling on electrostatic potential in calculating direct tunneling gate current in deep submicron MOSFETs [PDF]
, 2002 We investigate the validity of the assumption of neglecting carrier tunneling effects on self-consistent electrostatic potential in calculating direct tunneling gate current in deep submicron MOSFETs. Comparison between simulated and experimental results
Haque, A, Hakim, MMA
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Integration of Low‐Voltage Nanoscale MoS2 Memristors on CMOS Microchips
Advanced Functional Materials, EarlyView.This article presents the first monolithic integration of nanoscale MoS2‐based memristors into the back‐end‐of‐line of foundry‐fabricated CMOS microchips in a one‐transistor‐one‐resistor (1T1R) architecture. The MoS2‐based 1T1R cells exhibit forming‐free, nonvolatile resistive switching with ultra‐low operating voltages, low cycle‐to‐cycle variability ...
Jimin Lee +16 more
wiley +1 more source
Reliability of repetitively avalanched wire-bonded low-voltage discrete power trench n-MOSFETs [PDF]
, 2011 This paper, for the first time, investigates the reliability of wire-bonded low-voltage discrete power trench n-MOSFETs that have been subjected to repetitive unclamped inductive switching (RUIS).
Ian Kennedy +7 more
core +1 more source
Self‐Healing and Stretchable Synaptic Transistor
Advanced Functional Materials, EarlyView.A self‐healing stretchable synaptic transistor (3S‐T) is realized using a p‐PVDF‐HFP‐DBP/PDMS‐MPU‐IU bilayer as gate insulator, where dipole‐dipole interaction enhances polarization to achieve a large memory window. Leveraging its neuronal biomimicry, the synaptic transistor demonstrates electrically compatibility with the biological brain. Furthermore,
Hyongsuk Choo +10 more
wiley +1 more source
SiGe p-channel MOSFETs with tungsten gate [PDF]
, 1999 A self-aligned SiGe p-channel MOSFET tungsten gate process with 0.1 μm resolution is demonstrated. Interface charge densities of MOS capacitors realised with the low pressure sputtered tungsten process are comparable with thermally evaporated aluminium ...
Wilkinson, C.D.W. +5 more
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Advanced Materials, EarlyView.The perspective presents an integrated view of neuromorphic technologies, from device physics to real‐time applicability, while highlighting the necessity of full‐stack co‐optimization. By outlining practical hardware‐level strategies to exploit device behavior and mitigate non‐idealities, it shows pathways for building efficient, scalable, and ...
Kapil Bhardwaj +8 more
wiley +1 more source
High quality Schottky contacts for limiting leakage currents in Ge-based Schottky barrier MOSFETs [PDF]
, 2009 Schottky barrier (SB) Ge channel MOSFETs suffer from high drain-body leakage at the required elevated substrate doping concentrations to suppress source-drain leakage.
Husain, M.K., Li, X., de Groot, C.H.
core +1 more source