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3D Charge Trap NAND Flash Memories
2016This chapter starts off with 2 vertical channel architectures named BiCS (Bit Cost Scalable) and P-BiCS (Pipe-Shaped BiCS), respectively. BiCS was proposed for the first time by Toshiba in 2007, and another version called P-BiCS was presented in 2009 to improve retention, source selector performances and source line resistance.
Luca Crippa, Rino Micheloni
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2009
Les mémoires non-volatiles et plus spécialement les mémoires Flash sont de plus en plus utilisées dans le contexte SoC. Cet article présente une étude préliminaire des mécanismes de défaillances pouvant affecter les mémoires Flash NAND.
Mauroux, Pierre-Didier +5 more
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Les mémoires non-volatiles et plus spécialement les mémoires Flash sont de plus en plus utilisées dans le contexte SoC. Cet article présente une étude préliminaire des mécanismes de défaillances pouvant affecter les mémoires Flash NAND.
Mauroux, Pierre-Didier +5 more
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Evolution of NAND Flash Memory Interface
2007In this paper, we describe the basics of NAND flash memory and describe the evolution of its interface to facilitate easy integration, to provide high bandwidth, to offer disk-like interface, and/or to guarantee interoperability.
Sang Lyul Min +2 more
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Reliability issues of NAND Flash memories
2010The continuous demand for NAND flash memories with higher performance and storage capabilities pushes the manufactures towards the limits of present technologies and to explore new solutions, both from the physical and the architectural point of view.
C. Zambelli, A. Chimenton, P. Olivo
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Reliability of NAND Flash Memories
2010The continuous demand for NAND flash memories with higher performance and storage capabilities pushes the manufactures towards the limits of present technologies and to explore new solutions, both from the physical and the architectural point of view. The memory reliability represents one of the major antagonist towards this un-stoppable technological ...
ZAMBELLI, Cristian +2 more
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3D VG-Type NAND Flash Memories
2016The common feature among the different 3D NAND solutions is constituted by very deep vertical (z direction) etching steps that define the Flash cells geometries simultaneously. Transistor geometries are formed by the deep trench through a multiple polysilicon/oxide stack.
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