As data storage demands continue to grow, ensuring the reliability of NAND flash devices after a large number of Program/Erase (P/E) cycles have elapsed has become a critical requirement.
G. Achala +3 more
doaj +1 more source
Memcapacitor Crossbar Array with Charge Trap NAND Flash Structure for Neuromorphic Computing. [PDF]
Hwang S, Yu J, Song MS, Hwang H, Kim H.
europepmc +1 more source
NAND Flash Memory Characterization
The NAND technology has become a popular research area and implementation choice due to its non-volatile flash memory characteristics. There are many engineering challenges when it comes to NAND technology. Some of the limiting factors are reducing the transistor width and increasing read and write performance. The device physics for NAND floating gate
openaire +1 more source
This paper proposes a simple yet effective scheme for NAND Flash memories that employ on‐chip microcontroller units (MCUs) to manage internal array operations.
Geonu Kim
doaj +1 more source
A Novel Program Scheme for Z-Interference Improvement in 3D NAND Flash Memory. [PDF]
Jia J, Jin L, Jia X, You K.
europepmc +1 more source
Investigation of Erase Cycling Induced Joint Dummy Cell Disturbance in Dual-Deck 3D NAND Flash Memory. [PDF]
You K, Jin L, Jia J, Huo Z.
europepmc +1 more source
Self-Adaption of the GIDL Erase Promotes Stacking More Layers in 3D NAND Flash. [PDF]
Yang T, Zhang B, Wang Q, Jin L, Xia Z.
europepmc +1 more source
Effects of Poly-Si Grain Boundary on Retention Characteristics under Cross-Temperature Conditions in 3-D NAND Flash Memory. [PDF]
An U +6 more
europepmc +1 more source
Estimation method for bit upset ratio of NAND flash memory induced by heavy ion irradiation
In order to estimate the bit upset ratio of NAND flash memory induced by heavy ion irradiation, starting from the physical mechanism of the bit upset of NAND flash memory, an analytical model based on statistical methods was developed to describe the ...
Jiangkun Sheng +9 more
doaj +1 more source
Investigation of Program Efficiency Overshoot in 3D Vertical Channel NAND Flash with Randomly Distributed Traps. [PDF]
Park C +5 more
europepmc +1 more source

