Wordline Input Bias Scheme for Neural Network Implementation in 3D-NAND Flash. [PDF]
Hwang H, Kim G, Yu D, Kim H.
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Band and Field Coengineered Charge Trap Memristor via Au Nanoparticle Layer for Programming Speed Enhancement. [PDF]
Kim G +6 more
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Origin of the Temperature Dependence of Gate-Induced Drain Leakage-Assisted Erase in Three-Dimensional nand Flash Memories. [PDF]
Refaldi DG +4 more
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Ferroelectric NAND for efficient hardware bayesian neural networks. [PDF]
Song M +10 more
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A full-featured 2D flash chip enabled by system integration. [PDF]
Liu C +13 more
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Recent advances in ferroelectric materials, devices, and in-memory computing applications. [PDF]
Hwang H, Youn S, Kim H.
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Analysis of the Ambipolar Conduction of Tin Monoxide Thin-Film Transistors with Indium Tin Oxide Electrodes. [PDF]
Mun SA +8 more
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Temperature Gradients as a Data Storage Principle. [PDF]
Schoenmaker J, Martins PG, Teixeira JC.
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Progress of emerging non-volatile memory technologies in industry. [PDF]
Hellenbrand M +2 more
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Decoupling polarization and coercive field in AlScN/AlN/AlScN stack for enhanced performance in ferroelectric thin-film transistors. [PDF]
Kim KD +9 more
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