Design of a spin-wave majority gate employing mode selection
The design of a microstructured, fully functional spin-wave majority gate is presented and studied using micromagnetic simulations. This all-magnon logic gate consists of three-input waveguides, a spin-wave combiner and an output waveguide.
Brächer, Thomas +5 more
core +1 more source
Emerging Memory and Device Technologies for Hardware‐Accelerated Model Training and Inference
This review investigates the suitability of various emerging memory technologies as compute‐in‐memory hardware for artificial intelligence (AI) applications. Distinct requirements for training‐ and inference‐centric computing are discussed, spanning device physics, materials, and system integration.
Yoonho Cho +6 more
wiley +1 more source
High-Speed and Cost-Efficient NAND Logic Gate Using a Single SOA-DI Configuration
In this study, we propose a novel design for a NAND gate using a single semiconductor optical amplifier (SOA) followed by a delay interferometer (DI).
Amer Kotb +3 more
doaj +1 more source
Silicon Nitride Resistive Memories
Amorphous SiNx is an attractive resistance switching material for ReRAM applications due to its physicochemical properties, such as humidity resistance, low oxygen diffusivity, and is used as a metal diffusion blocker. By modifying the ratio between N and Si atoms, the microstructure of the SiNx is affected, rendering it possible to change the ...
Alexandros‐Eleftherios Mavropoulis +7 more
wiley +1 more source
Phase substitution of spare converter for a failed one of parallel phase staggered converters [PDF]
Failure detection and substitution of a spare module is provided in a system having a plurality of phase staggered modules connected in parallel to deliver regulated voltage from an unregulated source.
Mclyman, W. T., Wester, G. W.
core +1 more source
Physics‐Based Compact Modeling of Advanced 3D Nanoscale Vertical NAND Flash Memory
For advanced 3D NAND flash memory, a unified compact model for SPICE is proposed that spans from the intrinsic unit cell to the full string and captures the electrostatic coupling with adjacent inhibit strings. It can successfully predict read behavior, program/erase dynamics, and interactions between neighboring cells, reflecting array‐level behavior ...
Ilho Myeong, Seonho Shin, Ickhyun Song
wiley +1 more source
Increasing Flash Memory Lifetime by Dynamic Voltage Allocation for Constant Mutual Information [PDF]
The read channel in Flash memory systems degrades over time because the Fowler-Nordheim tunneling used to apply charge to the floating gate eventually compromises the integrity of the cell because of tunnel oxide degradation.
Chen, Tsung-Yi +2 more
core +1 more source
Hardware‐Based On‐Chip Learning Using a Ferroelectric AND‐Type Array With Random Synaptic Weights
This work demonstrates an energy‐efficient on‐chip learning system using an Metal‐Ferroelectric‐Insulator‐Semiconductor FeAND synaptic array. By employing a feedback alignment scheme with a separate backward array using fixed random weights, the system overcomes directional limitations of AND‐type arrays and achieves robust, low‐power learning suitable
Minsuk Song +8 more
wiley +1 more source
Testability enhancement of a basic set of CMOS cells [PDF]
Testing should be evaluated as the ability of the test patterns to cover realistic faults, and high quality IC products demand high quality testing. We use a test strategy based on physical design for testability (to discover both open and short faults ...
Bruls +20 more
core +3 more sources
Additively manufacturable micro-mechanical logic gates. [PDF]
Early examples of computers were almost exclusively based on mechanical devices. Although electronic computers became dominant in the past 60 years, recent advancements in three-dimensional micro-additive manufacturing technology provide new fabrication ...
Chizari, Samira +6 more
core +2 more sources

