Results 161 to 170 of about 5,324 (209)
Some of the next articles are maybe not open access.

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2014
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  +8 more sources

Recovery and universality in NBTI

Microelectronics Reliability, 2014
Abstract The fast recovery behavior in negative bias temperature instability (NBTI) in SiON gate p-type metal–oxide–silicon field effect transistors was investigated. The fast recovery is due to the hole detrapping from the K-center ( N 3 Si , where denotes a dangling bond).
openaire   +1 more source

NBTI-Aware Synthesis of Digital Circuits

2007 44th ACM/IEEE Design Automation Conference, 2007
Negative bias temperature instability (NBTI) in PMOS transistors has become a major reliability concern in nanometer scale design, causing the temporal degradation of the threshold voltage of the PMOS transistors, and the delay of digital circuits. A novel method to characterize the delay of every gate in the standard cell library, as a function of the
Sanjay V. Kumar   +2 more
openaire   +2 more sources

NBTI Degradation and Recovery in Analog Circuits: Accurate and Efficient Circuit-Level Modeling

open access: yesIEEE Transactions on Electron Devices, 2019
S.1662-1668We investigate the NBTI degradation and recovery of pMOSFETs under continuously varying analog-circuit stress voltages, and thereby generalize existing digital-stress NBTI studies.
Tibor Grässer   +2 more
exaly   +2 more sources

NBTI - evening discussion

IEEE International Integrated Reliability Workshop Final Report, 2003, 2003
Four topics were discussed: (1) Technology Trends in NBTI: The discussion here centered on how the process technology options can reduce NBTI by optimizing the N,H, and B concentrations at the gate oxide interface. There were some contradicting results which were reported on Deuterium.
S.J. Wen, H. Puchner
openaire   +1 more source

Ultrafast Measurement on NBTI

IEEE Electron Device Letters, 2009
We combine customary pulsed I- V setup with a simple linear drain-current correction method to provide a possible standard for NBTI characterization. The method is implemented using standard equipment and yet is able to achieve sub-100-ns delay, the shortest reported to date for a wafer-level setup.
G.A. Du, D.S. Ang, Z.Q. Teo, Y.Z. Hu
openaire   +1 more source

NBTI and PBTI in HKMG

2013
As the CMOS technology nodes progress aggressively into “nano” era, introduction of High-k Metal gate (HKMG) has became key to maintain the scaling trend. Much effort has been devoted to understand the reliability aspects of HKMG over the last decade.
Kai Zhao   +3 more
openaire   +1 more source

NBTI and Concurrent HCI-NBTI Degradation of 65 nm SOI PMOSFETs

2007 IEEE International SOI Conference, 2007
Body contacted (BC) core logic/high speed (HS) and input/output (I/O) SOI PMOSFETs from 65 nm technology are shown to have higher degradation than the counterpart floating body (FB) devices under NBTI stress. It is also observed that concurrent HCI-NBTI (hot-carrier injection-negative bias temperature instability) leads to worst case degradation for ...
Rahul Mishra   +3 more
openaire   +1 more source

Phase Space Based NBTI Model

2013
A phase space based NBTI model that relies upon the well-known reaction-diffusion model is introduced. Temporal shift in threshold voltage and a new parameter called “healability” are used to characterize the state of the NBTI effect. The NBTI degradation is then simulated as a trace of the interpolated characterization parameters. Thereby, healability
Eilers R.   +4 more
openaire   +2 more sources

?????????????? ??????????????????????????-?????????????????????? ?????????????????? ?? ?????????????????????? ?????????????????????????????? ?????????????????????????? ?????????????????????? ???? ?????????????????????????????? ???????????????? ???????????? NbTi

2017
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Szymczak, R.   +5 more
openaire   +1 more source

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