Investigation of Negative Bias Temperature Instability Effect in Nano PDSOI PMOSFET [PDF]
The Negative Bias Temperature Instability (NBTI) effect of partially depleted silicon-on-insulator (PDSOI) PMOSFET based on 130 nm is investigated. First, the effect of NBTI on the IV characteristics and parameter degradation of T-Gate PDSOI PMOSFET was ...
Yafang Yang +4 more
doaj +5 more sources
A Weighted NBTI/HCD Coupling Model in Full VG/VD Bias Space with Applications to SRAM Aging Simulation [PDF]
In this paper, a coupled negative bias temperature instability (NBTI)/hot carrier degradation (HCD) failure model is proposed on the 2-D voltage plane for aging simulation of SRAM circuits.
Zhen Chai, Zhenyu Wu
doaj +2 more sources
Impact of Nitridation on Bias Temperature Instability and Hard Breakdown Characteristics of SiON MOSFETs [PDF]
We study how nitridation, applied to SiON gate layers, impacts the reliability of planar metal-oxide-semiconductor field effect transistors (MOSFETs) subjected to negative and positive bias temperature instability (N/PBTI) as well as hard breakdown (HBD)
Stanislav Tyaginov +12 more
doaj +2 more sources
Research on the Coupling Effect of NBTI and TID for FDSOI pMOSFETs [PDF]
The coupling effect of negative bias temperature instability (NBTI) and total ionizing dose (TID) was investigated by simulation based on the fully depleted silicon on insulator (FDSOI) PMOS. After simulating the situation of irradiation after NBT stress,
Hao Wei +6 more
doaj +2 more sources
Implementation of Aging Mechanism Analysis and Prediction for XILINX 7-Series FPGAs with a 28-nm Process [PDF]
Commercial off-the-shelf (COTS) field-programmable gate arrays (FPGAs) with a 28-nm process have become popular devices for computing systems. Although current generation FPGAs have advantages over previous models, the phenomenon of circuit aging has ...
Zeyu Li +4 more
doaj +2 more sources
Enhanced soft error resilience of NBTI-tolerant dual mode Schmitt trigger circuit [PDF]
A dual-mode inverting Schmitt trigger (DM-IST) circuit is presented. The proposed DM-IST circuit is configured with a single PMOS in pull-up and five NMOS in pull-down networks to reduce the effect of negative bias temperature instability (NBTI) on the ...
Aryan Kannaujiya, Ambika Prasad Shah
doaj +2 more sources
Intelligence prediction of integrated circuit reliability based on SSA-LSTM fusion architecture. [PDF]
The relentless scaling of integrated circuits (ICs) into the nanoscale regime has intensified critical reliability challenges, such as Negative Bias Temperature Instability (NBTI), which manifests primarily as a progressive shift in the transistor ...
Ying Qian +3 more
doaj +2 more sources
Impact of Channel Thickness on the NBTI Behaviors in the Ge-OI pMOSFETs With Al2O3/GeOx Gate Stacks
The impact of channel thickness on the negative-bias temperature instability (NBTI) behaviors has been studied for the Germanium-on-Insulator (Ge-OI) pMOSFETs. It is found that the permanent and recoverable defects are generated simultaneously during the
Yu Sun +7 more
doaj +1 more source
The degradation mechanisms for pMOSFETs from a 130 nm partially-depleted silicon on insulator (PDSOI) technology under the combined effects of total ionizing dose (TID) and negative bias temperature instability (NBTI) are investigated.
Chao Peng +6 more
doaj +1 more source
Countermeasures against NBTI degradation on 6T-SRAM cells [PDF]
In current process technologies, NBTI (negative bias temperature instability) has the most severe aging effect on static random access memory (SRAM) cells. This degradation effect causes loss of stability.
E. Glocker +2 more
doaj +1 more source

