Results 31 to 40 of about 204 (157)

Achieving Exceptional Stability in Self‐Aligned Coplanar Amorphous Oxide Thin‐Film Transistors through Hydrogen Scavenger Layer

Small Structures, Volume 6, Issue 9, September 2025.
Hydrogen infiltration undermines self‐aligned oxide thin‐film transistors stability. A MoTi hydrogen‐scavenging layer is introduced that actively captures and immobilizes hydrogen throughout the device stack. Electron spin resonance and transient current stress, channel breakdown analyzes confirm reduced hydrogen‐related defects and enhanced electrical
I. Sak Lee, Kyungmoon Kwak, Jae Won Na, Hyun Jae Kim   +3 more
wiley   +1 more source

NBTI-Aware Transient Fault Rate Analysis Method for Logic Circuit Based on Probability Voltage Transfer Characteristics

Algorithms, 2016
The reliability of Very Large Scale Integration (VLSI) circuits has become increasingly susceptible to transient faults induced by environmental noise with the scaling of technology.
Zhiming Yang, Junbao Li, Yang Yu, Xiyuan Peng   +3 more
doaj   +1 more source

Characterizing the Effects of Intermittent Faults on a Processor for Dependability Enhancement Strategy

The Scientific World Journal, Volume 2014, Issue 1, 2014., 2014
As semiconductor technology scales into the nanometer regime, intermittent faults have become an increasing threat. This paper focuses on the effects of intermittent faults on NET versus REG on one hand and the implications for dependability strategy on the other.
Chao(Saul) Wang, Zhong-Chuan Fu, Hong-Song Chen, Dong-Sheng Wang, J. Shu, F. Yu   +5 more
wiley   +1 more source

Dopant Diffusion‐Induced Dielectric Breakdown: Stacked Dielectric Reliability on Heavily Doped Polysilicon

Advanced Electronic Materials, Volume 11, Issue 12, August 6, 2025.
This study reveals a novel failure mode in SiO₂/Si₃N₄ stacked capacitors, where dopant diffusion leads to interfacial oxide thinning, reducing dielectric breakdown voltage. Experimental results show that n type capacitors exhibit superior reliability, whereas p type capacitors fail rapidly.
Shuo Wang, Zebin Kong, Jie Zhao, Shukai Guan, Ranran Zhao, Anan Ju, Kunshu Wang, Pengfei Lian   +7 more
wiley   +1 more source

The Improvement of Reliability of High‐k/Metal Gate pMOSFET Device with Various PMA Conditions

Active and Passive Electronic Components, Volume 2012, Issue 1, 2012., 2012
The oxygen and nitrogen were shown to diffuse through the TiN layer in the high‐k/metal gate devices during PMA. Both the oxygen and nitrogen annealing will reduce the gate leakage current without increasing oxide thickness. The threshold voltages of the devices changed with various PMA conditions.
Yi-Lin Yang, Wenqi Zhang, Chi-Yun Cheng, Wen-kuan Yeh, Kuan-Wei Lee   +4 more
wiley   +1 more source

Analysis of Bias Temperature Instability in Peripheral CMOS Devices for Low-Temperature Memory Applications

IEEE Access
In this study, the bias temperature instability (BTI) of peripheral complementary metal–oxide semiconductor devices in a cell-on-peri (COP) structure is investigated under cryogenic conditions. First, positive BTI (PBTI) in the nMOSFET is found to
Jung Rae Cho, Seungwon Go, Jingyu Park, Tae Jun Yang, Seonhaeng Lee, Namhyun Lee, Dong Keun Lee, Yoon Kim, Myounggon Kang, Rock-Hyun Baek, Changhyun Kim, Sangwan Kim, Dae Hwan Kim   +12 more
doaj   +1 more source

Investigation and Improvement of the Bias Temperature Instability in Carbon Nanotube Transistors

Advanced Electronic Materials, Volume 11, Issue 4, April 2025.
In this work, the reliability of BTI in top‐gate CNT FETs under a wide range of temperatures is investigated firstly. The CNT devices not only exhibit a high on/off current ratio (Ion/Ioff, ≈105) and a low subthreshold swing (SS) ranging from 200 to 400 K, but also the threshold voltage (Vth) shifts caused by BTI become 2–3 times smaller than previous ...
Yifu Sun, Peng Lu, Lingyu Zhang, Yu Cao, Lan Bai, Li Ding, Jie Han, Chiyu Zhang, Maguang Zhu, Zhiyong Zhang   +9 more
wiley   +1 more source

Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations

VLSI Design, Volume 2010, Issue 1, 2010., 2010
The complexity of timing optimization of high‐performance circuits has been increasing rapidly in proportion to the shrinking CMOS device size and rising magnitude of process variations. Addressing these significant challenges, this paper presents a timing optimization algorithm for CMOS dynamic logic and a Path Oriented IN Time (POINT) optimization ...
Kumar Yelamarthi, Chien-In Henry Chen, Ethan Farquhar   +2 more
wiley   +1 more source

Power/Energy Minimization Techniques for Variability-Aware High-Performance 16-nm 6T-SRAM

IEEE Access, 2016
Power and energy minimization is a critical concern for the battery life, reliability, and yield of many minimum-sized SRAMs. In this paper, we extend our previously proposed hybrid analytical-empirical model for minimizing and predicting the delay and ...
Jeren Samandari-Rad, Richard Hughey
doaj   +1 more source

Reliability challenges of gate dielectric materials in transistors

Information &Functional Materials, Volume 2, Issue 1, Page 62-92, March 2025.
We summarize the advantages and challenges of different dielectrics that are applicable to several mainstream channel materials, including Si, SiC, GaN, and 2D materials. The dielectrics materials include oxides such as SiO2, HfO2, and Al2O3 for conventional transistors, as well as fluorides, van der Waals insulators, and Perovskites, which are ...
Ting‐Wei Liu, Zhe Zhao, Ruyue Cao, Yue‐Yang Liu, Xiangwei Jiang   +4 more
wiley   +1 more source