Results 51 to 60 of about 8,396,680 (189)

Models of source/drain bias on negative bias temperature instability

, 2006
This paper discusses the influence of source/drain (S/D) bias on negative bias temperature instability (NBTI) in pMOS devices. It is found that with the S/D bias increase, the NBTI degradation is initially reduced, but it increases with higher S/D bias ...
Kang, J.F., M.. Liao, Liao, C.C., Wong, Y.Y., Yan, B.G., Y.Y. Wong, Wong, W., Z.H. Gan, C.C. Liao, W. Wong, J.F. Kang, B.G. Yan, Wang, J.P., J.P. Wang, Gan, Z.H., Liao, M.   +15 more
core   +1 more source

Analysis and EOT Scaling on Top‐ and Double‐Gate 2D CVD‐Grown Monolayer MoS2 FETs

Advanced Electronic Materials, Volume 10, Issue 11, November 2024.
This study investigates double‐gate chemical vapor deposition (CVD)‐grown monolayer molybdenum disulfide (1L‐MoS2) field‐effect‐transistors (FETs) and elucidates the mechanisms for improvements compared to single top‐gated devices. It also reports on the impact of equivalent oxide thickness (EOT) scaling on subthreshold swing (SS) and gate hysteresis ...
Naim Hossain Patoary, Fahad Al Mamun, Jing Xie, Tibor Grasser, Ivan Sanchez Esqueda   +4 more
wiley   +1 more source

Design of a reliability methodology: Modelling the influence of temperature on gate Oxide reliability [PDF]

, 2007
An Integrated Reliability Methodology (IRM) is presented that encompasses the changes that technology growth has brought with it and includes several new device degradation models.
Owens, Gethin Lloyd
core  

Threshold voltage instability of SiC MOSFETs under very‐high temperature and wide gate bias

IET Power Electronics, Volume 17, Issue 15, Page 2393-2404, 25 November 2024.
This article presents a detailed investigation of the threshold voltage degradation of commercial SiC MOSFETs due to the application of high temperature and DC bias stress in a more comprehensive voltage range and a higher temperature range. Abstract Threshold voltage (VTH) instability affects the reliability of silicon carbide (SiC) MOSFETs.
Cong Chen, Yumeng Cai, Peng Sun, Zhibin Zhao   +3 more
wiley   +1 more source

A novel negative bias temperature instability model for nanoscale finfet

, 2009
This paper presents both static and dynamic NBTI Negative Bias Temperature Instability model based on the novel Reaction-Trapping theory. The accuracy of the proposed is greatly improved comparing to the classical Reaction-Diffusion theory, and the ...
Ma, Chenyue, Li, Bo, He, Frank, Zhang, Xing, Bo Li, Xing Zhang, Frank He, Chenyue Ma, Xinnan Lin, Lin, Xinnan   +9 more
core   +1 more source

DEFECTS FOR RANDOM TELEGRAPH NOISE AND NEGATIVE BIAS TEMPERATURE INSTABILITY [PDF]

Random Telegraphy Noise (RTN) and Negative Bias Temperature Instability (NBTI) are two important sources of device instability. Their relation is not fully understood and is investigated in this work.
Duan, M, Ji, Z, Zhang, JF, Zhang, WD
core   +3 more sources

Research progress and challenges in the reliability of SiGe channel CMOS device

Gongneng cailiao yu qijian xuebao
As complementary metal-oxide-semiconductor (CMOS) technology scales down to the 5 nm node and beyond, SiGe channels have become a promising solution for high-performance p-type field-effect transistor (pFET) due to their superior hole mobility, with ...
Guoqixin HUANG, Yiming QU, Choonghyun LEE   +2 more
doaj   +1 more source

Review—Extremely Thin Amorphous Indium Oxide Transistors

Advanced Materials, Volume 36, Issue 9, March 1, 2024.
Reducing the thickness of indium oxide, enabled by atomic layer deposition (ALD) process, can tune its material properties to achieve high performance devices beyond the capabilities of conventional oxide semiconductors. In this work, the history leading to the re‐emergence of indium oxide, its fundamental material properties, growth techniques with a ...
Adam Charnas, Zhuocheng Zhang, Zehao Lin, Dongqi Zheng, Jie Zhang, Mengwei Si, Peide D. Ye   +6 more
wiley   +1 more source

New Model for Simulating Impact of Negative Bias Temperature Instability (NBTI) in CMOS Circuits [PDF]

, 2014
: Negative Bias Temperature Instability (NBTI) is commonly seen in p-channel transistors under negative gate voltages at an elevated temperature. The interface traps, oxide traps and NBTI mechanisms are discussed and their effect on circuit degradation ...

core  

Impact of Aging, Self-Heating, and Parasitics Effects on NSFET and CFET

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
This work presents a comparative analysis of complementary field-effect transistor (CFET) and nanosheet FET (NSFET) architectures, with a focus on self-heating effects (SHEs), negative bias temperature instability (NBTI), hot carrier degradation (HCD ...
Swati Deshwal, Sufia Shahin, Anirban Kar, Yogesh S. Chauhan, Hussam Amrouch   +4 more
doaj   +1 more source