Logical Resolving-Based Methodology for Efficient Reliability Analysis. [PDF]
Tang Z +7 more
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CMOS transistor scaling-down involves an increase in the manufacturing complexity and brings up reliability as a serious challenge to overcome in recent node technologies. In this context, it is mandatory to characterize and model the various failure mechanisms at the transistor level.
openaire +1 more source
Device and Circuit Co-Optimization of Split-Controlled Flip-Flops Against Aging Towards Low-Voltage Applications. [PDF]
Zhao Y, Tan J, Chen L, Zhu H, Sun Q.
europepmc +1 more source
Overcoming Ambient Drift and Negative-Bias Temperature Instability in Foundry Carbon Nanotube Transistors. [PDF]
Yu AC, Srimani T, Shulaker MM.
europepmc +1 more source
A Coupling Mechanism between Flicker Noise and Hot Carrier Degradations in FinFETs. [PDF]
Liu M +6 more
europepmc +1 more source
Improving stability in two-dimensional transistors with amorphous gate oxides by Fermi-level tuning. [PDF]
Knobloch T +9 more
europepmc +1 more source
Editorial for the Special Issue on MEMS/NEMS Devices and Applications, 3rd Edition. [PDF]
Dai ZX, Ono T, Dai CL.
europepmc +1 more source
Evaluation on Temperature-Dependent Transient VT Instability in p-GaN Gate HEMTs under Negative Gate Stress by Fast Sweeping Characterization. [PDF]
Wang R +10 more
europepmc +1 more source
Stability and Reliability of van der Waals High-κ SrTiO<sub>3</sub> Field-Effect Transistors with Small Hysteresis. [PDF]
Sattari-Esfahlan SM +8 more
europepmc +1 more source
Near-zero hysteresis van der Waals MnAl<sub>2</sub>S<sub>4</sub> field-effect transistors with low minimal threshold voltage degradation and high thermal stability. [PDF]
Sattari-Esfahlan SM +9 more
europepmc +1 more source

