Results 41 to 50 of about 8,396,680 (189)

Dynamic CMOS Load Balancing and Path Oriented in Time Optimization Algorithms to Minimize Delay Uncertainties from Process Variations

VLSI Design, Volume 2010, Issue 1, 2010., 2010
The complexity of timing optimization of high‐performance circuits has been increasing rapidly in proportion to the shrinking CMOS device size and rising magnitude of process variations. Addressing these significant challenges, this paper presents a timing optimization algorithm for CMOS dynamic logic and a Path Oriented IN Time (POINT) optimization ...
Kumar Yelamarthi, Chien-In Henry Chen, Ethan Farquhar   +2 more
wiley   +1 more source

Analysis of Bias Temperature Instability in Peripheral CMOS Devices for Low-Temperature Memory Applications

IEEE Access
In this study, the bias temperature instability (BTI) of peripheral complementary metal–oxide semiconductor devices in a cell-on-peri (COP) structure is investigated under cryogenic conditions. First, positive BTI (PBTI) in the nMOSFET is found to
Jung Rae Cho, Seungwon Go, Jingyu Park, Tae Jun Yang, Seonhaeng Lee, Namhyun Lee, Dong Keun Lee, Yoon Kim, Myounggon Kang, Rock-Hyun Baek, Changhyun Kim, Sangwan Kim, Dae Hwan Kim   +12 more
doaj   +1 more source

Reliability challenges of gate dielectric materials in transistors

Information &Functional Materials, Volume 2, Issue 1, Page 62-92, March 2025.
We summarize the advantages and challenges of different dielectrics that are applicable to several mainstream channel materials, including Si, SiC, GaN, and 2D materials. The dielectrics materials include oxides such as SiO2, HfO2, and Al2O3 for conventional transistors, as well as fluorides, van der Waals insulators, and Perovskites, which are ...
Ting‐Wei Liu, Zhe Zhao, Ruyue Cao, Yue‐Yang Liu, Xiangwei Jiang   +4 more
wiley   +1 more source

Plasma‐Induced Damage on the Reliability of Hf‐Based High‐k/Dual Metal‐Gates Complementary Metal Oxide Semiconductor Technology

International Journal of Plasma Science and Engineering, Volume 2009, Issue 1, 2009., 2009
This study examines the effects of plasma‐induced damage (PID) on Hf‐based high‐k/dual metal‐gates transistors processed with advanced complementary metal‐oxide‐semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates that thinning the gate dielectric reduces the impact of damage on transistor ...
Wu-Te Weng, Yao-Jen Lee, Horng-Chih Lin, Tiao-Yuan Huang, Paul K. Chu   +4 more
wiley   +1 more source

Temperature‐Driven Performance and Reliability Trade‐Offs in 7 nm FinFET‐Based Dynamic Comparators

IET Circuits, Devices &Systems, Volume 2025, Issue 1, 2025.
Both circuit performance and long‐term reliability are significantly impacted by the combined effects of temperature‐induced drive current fluctuations and self‐heating in FinFET devices. The performance of a three‐stage rail‐to‐rail dynamic comparator based on a 7 nm FinFET is examined in this work, taking into account the effects of thermal changes ...
MD Badhesha, J. Ajayan, Asisa Kumar Panigrahy, Amit Krishna Dwivedi, Ravi Gangwar   +4 more
wiley   +1 more source

An analytical model for negative bias temperature instability

, 2010
Negative bias temperature instability (NBTI) has become one of the major limiters for product lifetime, and various models have been proposed in order to explain NBTI. In this paper, an analytical model for DC NBTI and AC NBTI is proposed.
Gang Du, Wang, Shengcheng, Du, Gang, Liu, Xiaoyan, Shengcheng Wang, Xiaoyan Liu   +5 more
core   +1 more source

Aging Analysis and Degradation Prediction of PLL Circuits in 14-nm FinFET Technology

IEEE Journal of the Electron Devices Society
This work investigates the reliability and aging predictions in a 14-nm FinFET-based analog circuit under high-temperature conditions. Aging simulations and accelerated aging tests were carried out on key devices of phase-locked loop (PLL) circuits, with
Meng Li, Xin Xu, Xianghui Li, Yunpeng Li, Yiqun Shi, Qingqing Sun, Hao Zhu   +6 more
doaj   +1 more source

Power/Energy Minimization Techniques for Variability-Aware High-Performance 16-nm 6T-SRAM

IEEE Access, 2016
Power and energy minimization is a critical concern for the battery life, reliability, and yield of many minimum-sized SRAMs. In this paper, we extend our previously proposed hybrid analytical-empirical model for minimizing and predicting the delay and ...
Jeren Samandari-Rad, Richard Hughey
doaj   +1 more source

A Review of Performance and Reliability Issues in D Flip‐Flops for Future Artificial Intelligence and Internet of Things Applications

IET Circuits, Devices &Systems, Volume 2025, Issue 1, 2025.
In this paper, various D flip‐flops (FFs) (DFFs) are studied and analyzed based on the performance and reliability effects of different architectures, technology, area, power, delay, and several other key performance parameters of DFFs. Based on these parameters, a few selected DFFs such as C2SFF, conditional‐bridging FF (CBFF)‐S, self‐shut‐off pulsed ...
Syeda Hurmath Juveria, R. Shashank, J. Ajayan, Amit Krishna Dwivedi, D. Nirmal, Shashikant Patil   +5 more
wiley   +1 more source

p-MOSFETにおけるNBTI(Negative Bias Temperature Instability)効果のモデル開発 [PDF]

, 2013
In the next 10 years, the dimension of semiconductor devices will scale towards 10nm. Consequently the reliability of ULSI circuits and systems faces enlarged challenges due to the introduction of the new materials and non-classical structures ...
Ma, Chenyue
core