Results 41 to 50 of about 204 (157)

Aging Analysis and Degradation Prediction of PLL Circuits in 14-nm FinFET Technology

IEEE Journal of the Electron Devices Society
This work investigates the reliability and aging predictions in a 14-nm FinFET-based analog circuit under high-temperature conditions. Aging simulations and accelerated aging tests were carried out on key devices of phase-locked loop (PLL) circuits, with
Meng Li, Xin Xu, Xianghui Li, Yunpeng Li, Yiqun Shi, Qingqing Sun, Hao Zhu   +6 more
doaj   +1 more source

Temperature‐Driven Performance and Reliability Trade‐Offs in 7 nm FinFET‐Based Dynamic Comparators

IET Circuits, Devices &Systems, Volume 2025, Issue 1, 2025.
Both circuit performance and long‐term reliability are significantly impacted by the combined effects of temperature‐induced drive current fluctuations and self‐heating in FinFET devices. The performance of a three‐stage rail‐to‐rail dynamic comparator based on a 7 nm FinFET is examined in this work, taking into account the effects of thermal changes ...
MD Badhesha, J. Ajayan, Asisa Kumar Panigrahy, Amit Krishna Dwivedi, Ravi Gangwar   +4 more
wiley   +1 more source

A Review of Performance and Reliability Issues in D Flip‐Flops for Future Artificial Intelligence and Internet of Things Applications

IET Circuits, Devices &Systems, Volume 2025, Issue 1, 2025.
In this paper, various D flip‐flops (FFs) (DFFs) are studied and analyzed based on the performance and reliability effects of different architectures, technology, area, power, delay, and several other key performance parameters of DFFs. Based on these parameters, a few selected DFFs such as C2SFF, conditional‐bridging FF (CBFF)‐S, self‐shut‐off pulsed ...
Syeda Hurmath Juveria, R. Shashank, J. Ajayan, Amit Krishna Dwivedi, D. Nirmal, Shashikant Patil   +5 more
wiley   +1 more source

Analysis and EOT Scaling on Top‐ and Double‐Gate 2D CVD‐Grown Monolayer MoS2 FETs

Advanced Electronic Materials, Volume 10, Issue 11, November 2024.
This study investigates double‐gate chemical vapor deposition (CVD)‐grown monolayer molybdenum disulfide (1L‐MoS2) field‐effect‐transistors (FETs) and elucidates the mechanisms for improvements compared to single top‐gated devices. It also reports on the impact of equivalent oxide thickness (EOT) scaling on subthreshold swing (SS) and gate hysteresis ...
Naim Hossain Patoary, Fahad Al Mamun, Jing Xie, Tibor Grasser, Ivan Sanchez Esqueda   +4 more
wiley   +1 more source

Research progress and challenges in the reliability of SiGe channel CMOS device

Gongneng cailiao yu qijian xuebao
As complementary metal-oxide-semiconductor (CMOS) technology scales down to the 5 nm node and beyond, SiGe channels have become a promising solution for high-performance p-type field-effect transistor (pFET) due to their superior hole mobility, with ...
Guoqixin HUANG, Yiming QU, Choonghyun LEE   +2 more
doaj   +1 more source

Threshold voltage instability of SiC MOSFETs under very‐high temperature and wide gate bias

IET Power Electronics, Volume 17, Issue 15, Page 2393-2404, 25 November 2024.
This article presents a detailed investigation of the threshold voltage degradation of commercial SiC MOSFETs due to the application of high temperature and DC bias stress in a more comprehensive voltage range and a higher temperature range. Abstract Threshold voltage (VTH) instability affects the reliability of silicon carbide (SiC) MOSFETs.
Cong Chen, Yumeng Cai, Peng Sun, Zhibin Zhao   +3 more
wiley   +1 more source

Impact of Aging, Self-Heating, and Parasitics Effects on NSFET and CFET

IEEE Journal on Exploratory Solid-State Computational Devices and Circuits
This work presents a comparative analysis of complementary field-effect transistor (CFET) and nanosheet FET (NSFET) architectures, with a focus on self-heating effects (SHEs), negative bias temperature instability (NBTI), hot carrier degradation (HCD ...
Swati Deshwal, Sufia Shahin, Anirban Kar, Yogesh S. Chauhan, Hussam Amrouch   +4 more
doaj   +1 more source

Review—Extremely Thin Amorphous Indium Oxide Transistors

Advanced Materials, Volume 36, Issue 9, March 1, 2024.
Reducing the thickness of indium oxide, enabled by atomic layer deposition (ALD) process, can tune its material properties to achieve high performance devices beyond the capabilities of conventional oxide semiconductors. In this work, the history leading to the re‐emergence of indium oxide, its fundamental material properties, growth techniques with a ...
Adam Charnas, Zhuocheng Zhang, Zehao Lin, Dongqi Zheng, Jie Zhang, Mengwei Si, Peide D. Ye   +6 more
wiley   +1 more source

Impact of process variations and long term degradation on 6T-SRAM cells [PDF]

Advances in Radio Science, 2007
In modern deep-submicron CMOS technologies voltage scaling can not keep up with the scaling of the dimensions of transistors. Therefore the electrical fields inside the transistors are not constant anymore, while scaling down the device area.
Th. Fischer, A. Olbrich, G. Georgakos, B. Lemaitre, D. Schmitt-Landsiedel   +4 more
doaj  

Effects of Fluorine on the NBTI Reliability and Low-Frequency Noise Characteristics of p-MOSFETs

IEEE Journal of the Electron Devices Society, 2018
The concurrent effect of fluorine implantation with various energy and dose on reliability and low-frequency noise characteristics of p-MOSFETs was investigated.
Sung-Kyu Kwon, Hyuk-Min Kwon, In-Shik Han, Jae-Hyung Jang, Sun-Ho Oh, Hyeong-Sub Song, Byoung-Seok Park, Yi-Sun Chung, Jung-Hwan Lee, Si-Bum Kim, Ga-Won Lee, Hi-Deok Lee   +11 more
doaj   +1 more source