Results 81 to 90 of about 8,396,680 (189)
CFET Beyond 3 nm: SRAM Reliability Under Design-Time and Run-Time Variability
IEEE Journal on Exploratory Solid-State Computational Devices and CircuitsThis work investigates the reliability of complementary field-effect transistors (CFETs) by addressing both design-time variability arising from process variations and run-time variability due to temperature and aging effects.
Sufia Shahin +5 more
doaj +1 more source
Bias Temperature Instability of Low Temperature Polycrystalline Silicon Thin-Film Transistor
, 2007 目前低溫複晶矽薄膜電晶體仍有需多問題需要解決，如漏電流的問題，以及我們對於複晶矽還有許多物理特性並不是十分的了解，而我們的研究方向就是低溫複晶矽薄膜電晶體之偏壓溫度不穩定性，這是屬於元件可靠度分析的範疇。在我們的論文裡，我們使用了不同的閘極偏壓，配合上不同的溫度以及不同的施以偏壓時間，其中包含了長時間與短時間，去做我們的元件偏壓溫度不穩定性實驗。藉由外在條件的不同，我們去觀察元件之後特性的變化。除了我們將試著去了解低溫複晶矽薄膜電晶體之電性之外，我們也閱讀相關的論文或研究報告，從這些已知的研究之中 ...
YE, JIA-HONG, 葉家宏
core
Impact of substrate bias on p-MOSFET negative bias temperature instability
, 2005 Negative Bias Temperature Instability(NBTI)of p-MOSFET is an important reliability issues for digital[1] as well as analog [2] CMOS circuits.Till date,characterization[3-9] and modelling [10-12] efforts to analyze NBTI machanism involve devices stressed ...
BHARATH KUMAR, P +5 more
core +2 more sources
NEGATIVE BIAS TEMPERATURE INSTABILITY STUDIES FOR ANALOG SOC CIRCUITS [PDF]
, 2012 Negative Bias Temperature Instability (NBTI) is one of the recent reliability issues in sub threshold CMOS circuits. NBTI effect on analog circuits, which require matched device pairs and mismatches, will cause circuit failure.
ABDUL LATIF, MOHD AZMAN
core
, 2005 It has been the intent of this work to investigate negative bias temperature instability of pMOSFET with ultra-thin gate dielectrics both theoretically and experimentally.
Tan, Shyue Seng
core +1 more source
, 2008 For Si O2 or SiON, negative bias temperature instability (NBTI) generally follows a power law. There is less information available for the NBTI of Hf stacks and it will be studied and compared with that of Si O2 in this work.
Zhang, J. F. +19 more
core +1 more source
Correlation of negative bias temperature instability and breakdown in HfO2/TiN gate stacks
, 2010 Both negative bias temperature instability (NBTI) and time dependent dielectric breakdown (TDDB) are two major reliability issues for long term performance of high-k gate stacks. In this work, these two degradation mechanisms were extensively analyzed to
Misra, D., Rahim, N.
core +1 more source
Negative Bias Temperature Instability And Charge Trapping Effects On Analog And Digital Circuit Reliability [PDF]
, 2007 Nanoscale p-channel transistors under negative gate bias at an elevated temperature show threshold voltage degradation after a short period of stress time.
Yu, Yixin
core
, 2009 Degradation of device parameters over the lifetime of a system is emerging as a significant threat to system reliability. Among the aging mechanisms, wearout resulting from Negative Bias Temperature Instability (NBTI) is of particular concern in deep ...
Wang, Wenping +8 more
core +1 more source
Impact of Negative Bias Temperature Instability on FPGAs
, 2005 In this sliide presentation the statistical impact of PMOS Negative Bias Temperature Instability (NBTI) degradation on circuit delay is reviewed. An on-board timing circuitry that was been developed to detect and measure timing delays in SRAM-based LUT ...
Burke, Gary +4 more
core