Results 201 to 210 of about 124,516 (258)

Label-free assessment of a microfluidic vessel-on-chip model with visible-light optical tomography reveals structural changes in vascular networks.

Lab Chip
Veerman D, Cuartas-Vélez C, Gensheimer T, van Dorp T, van der Meer A, Bosschaart N.   +5 more
europepmc   +1 more source

A Feedback Loop Driven by H3K18la and ASF1B via the LINC02732-miR-1291 Axis Promotes Hepatocellular Carcinoma Proliferation. [PDF]

Cells
Yu J, Xin L, Cui Y, Fan C, Yang Y, Zhang X.   +5 more
europepmc   +1 more source

GRNFormer: accurate gene regulatory network inference using graph transformer. [PDF]

Bioinformatics
Hegde A, Cheng J.
europepmc   +1 more source

3D Vessels-on-Chip using isogenic hiPSC-derived VSMCs reveal NOTCH3-driven alterations in brain small vessel disease. [PDF]

Stem Cell Reports
Vila Cuenca M, Tsikari T, Cerfontaine MN, Gallant JL, van den Hil FE, Bouma MJ, Dijkstra KL, Gravesteijn G, de Vries AAF, Mummery CL, Rutten JW, Lesnik Oberstein SAJ, Orlova VV.   +12 more
europepmc   +1 more source

Microcomb-enabled parallel self- calibration optical convolution streaming processor. [PDF]

Light Sci Appl
Wang J, Xu X, Zhu X, Xu Y, Chen S, Zhang H, Zheng Y, Li S, Bai Y, Liu Z, Morandotti R, Little BE, Chu ST, Lowery AJ, Moss DJ, Xu K.   +15 more
europepmc   +1 more source

A thermal resistance prediction model for heterogeneous integrated chips incorporating an AI-based BP neural network. [PDF]

Sci Rep
Li Y, Xu S, Guo L.
europepmc   +1 more source

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Network-on-Chip and Photonic Network-on-Chip Basic Concepts: A Survey

Journal of Electronic Testing: Theory and Applications (JETTA), 2023
Syed Maqsood Zia, Bahareh Asadi, Asghar Mohamadian   +2 more
exaly   +2 more sources

The CONNECT Network-on-Chip Generator

Computer, 2015
Efficiently supporting the communication needs of systems on chip with tens to hundreds of interacting modules requires a systematic and flexible network-on-chip (NoC) infrastructure. The freely available CONNECT generator lets users quickly navigate a range of design parameters to produce tailored NoC design instances in Verilog.
Michael K. Papamichael, James C. Hoe
exaly   +2 more sources

Routerless Network-on-Chip

2018 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2018
Traditional bus-based interconnects are simple and easy to implement, but the scalability is greatly limited. While router-based networks-on-chip (NoCs) offer superior scalability, they also incur significant power and area overhead due to complex router structures.
Fawaz Alazemi, Arash AziziMazreah, Bella Bose, Lizhong Chen   +3 more
openaire   +1 more source