Results 211 to 220 of about 124,516 (258)

Sensor Network-On-Chip

2007 International Symposium on System-on-Chip, 2007
In this paper, we present the sensor network-on-a-chip (SNOC) paradigm for designing robust and energy-efficient systems-on-a-chip (SOC). In this paradigm, computation in the presence of nanometer non-idealities such as process variations, leakage and noise is viewed as an estimation problem. Robust statistical signal processing theory is then employed
Girish Varatkar, Sriram Narayanan, Naresh R. Shanbhag, Douglas L. Jones   +3 more
openaire   +1 more source

The runahead network-on-chip

2016 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2016
With increasing core counts and higher memory demands from applications, it is imperative that networks-on-chip (NoCs) provide low-latency, power-efficient communication. Conventional NoCs tend to be over-provisioned for worst-case bandwidth demands leading to ineffective use of network resources and significant power inefficiency; average channel ...
Zimo Li, Joshua San Miguel, Natalie D. Enright Jerger   +2 more
openaire   +1 more source

Network-on-Chip for Turbo Decoders

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016
The multi-application specific instruction processor (ASIP) architecture is a promising candidate for flexible high-throughput turbo decoders. This brief proposes a network-on-chip (NoC) structure for multi-ASIP turbo decoders. The process of turbo decoding is studied, and the addressing patterns for turbo codes in long term evolution (LTE) and High ...
Yang, Qingqing, Zhou, Xiaofang, Sobelman, Gerald Edward, Li, Xinxin   +3 more
openaire   +2 more sources

Optical Interconnects for Network on Chip

2006 1st International Conference on Nano-Networks and Workshops, 2006
This paper resumes some state-of-the-art results of research in view of the realization of optical interconnects as physical link for Network on Chip (NoC). Emphasis is given in particular to amorphous Silicon technology for its actual technological compatibility with CMOS microchips.
Scandurra A., Lenzi M., Guerra R., Della Corte F. G., Nigro M. A.   +4 more
openaire   +2 more sources

Wireless on Networks-on-Chip

2013 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP), 2013
On-chip wireless interconnects are being investigated for applicability on network-on-chip systems of contemporary Multiprocessor Systems-on-chip (MPSoCs). Targeting both 2D and 3D semiconductor technologies, wireless interconnects are established with multiple antennas on the same die or couplers on the layers of a 3D IC package.
openaire   +1 more source

Layered Switching for Networks on Chip

2007 44th ACM/IEEE Design Automation Conference, 2007
We present and evaluate a novel switching mechanism called layered switching. Conceptually, the layered switching implements wormhole on top of virtual cut-through switching. To show the feasibility of layered switching, as well as to confirm its advantages, we conducted an RTL implementation study based on a canonical wormhole architecture.
Zhonghai Lu, Ming Liu 0011, Axel Jantsch
openaire   +1 more source

CDMA technique for Network-on-Chip

2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2012
A Code-Division Multiple Access (CDMA) based on-chip communication network is proposed in this paper. The proposed design features a novel encoding and decoding scheme for CDMA transmission which improves area, latency and power dissipation of the network on Chip (NoC).
Ahmed A. El Badry, Mohamed A. Abd El-Ghany   +1 more
openaire   +1 more source

Networks on Chips

2006
The design of today's semiconductor chips for various applications, such as telecommunications, poses various challenges due to the complexity of these systems. These highly complex systems-on-chips demand new approaches to connect and manage the communication between on-chip processing and storage components and networks on chips (NoCs) provide a ...
Benini, Luca, De Micheli, Giovanni, Bertozzi, Davide, Cidon, Israel, Goossens, Kees, Kim, Kwanho, Lee, Kangmin, Lee, Se Joong, Murali, Srinivasan, Yoo, Hoi Jun   +9 more
openaire   +2 more sources

Power efficient Networks on Chip

2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009), 2009
a low power switch design is proposed to achieve power-efficient Network on Chip (NoC). The proposed NoC switch reduces the power consumption of the Butterfly Fat Tree (BFT) architecture by 28 % as compared to the conventional BFT switch. Moreover, the power reduction technique is applied to different NoC architectures.
Mohamed A. Abd El-Ghany, Magdy A. El-Moursy, Darek Korzec, Mohammed Ismail 0001   +3 more
openaire   +1 more source

Networking on chip with platform FPGAs

Proceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT) (IEEE Cat. No.03EX798), 2004
This paper is concerned with networking at the chip level. Networks on chip have become a convenient focus for discussing the architecture of systems on chip, and design methodologies for such systems. One central question for such a focus concerns the extent to which it is useful or realistic just to scale down approaches used conventionally in larger-
Gordon J. Brebner, Delon Levi
openaire   +1 more source