Results 231 to 240 of about 132,536 (283)

Powering networks on chips

Proceedings of the 14th international symposium on Systems synthesis - ISSS '01, 2001
We consider systems on chips (SoCs) that will be designed and produced in five to ten years from today, with gate lengths in the range 50-100nm. We address the distinguishing features of a design methodology that aims at achieving reliable designs under the limitations of the interconnect technology.
Luca Benini, Giovanni De Micheli
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Energy-Efficient Network-On-Chip Design

2004
This chapter presents the latest advances in energy-efficient NoC design. Early NoC architectures are clearly power and area inefficient, thus calling for power optimization techniques. The chapter illustrates low power design techniques at several levels of abstraction in the NoC design process.
BENINI, LUCA, BERTOZZI, DAVIDE, G. De Micheli   +2 more
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Networks-on-Chip (NoC)

2011
The move to many-core system is expected to become the dominant trend in the near future. With technology scaling into nanoscale regime, hundreds and even thousands of intellectual property (IP) cores can be integrated into a single chip. How to provide efficient and reliable communication between these IP cores becomes a bit problem.
Bo Fu, Paul Ampadu
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Network on Chip Experiments

2018
The power estimation method is evaluated in the context of a network on chip communication infrastructure. The reference power consumption information is provided by post-layout gate-level simulations. On system level, the network on chip is modeled bit-accurately and cycle-accurate, wile the virtual platform contains also abstract models of the ...
Stefan Schuermans, Rainer Leupers
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Networks on Chips

2017
Networks implemented on single integrated circuit chips are important to present and future electronic technology. Different interconnection networks suitable for networks on chips are covered including stars, buses, meshes, torii, fat trees, butterfly fat trees, and octagon topologies. The architecture of nodes and switching alternatives are discussed.
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Network on Chip Aspects

2015
NoC infrastructure is composed of routers, NIC, and interconnects as shown in Fig. 2.1. Routers are connected with their neighbors using multiple number of interconnects. Each PE is connected to a local port of a router through a NIC. The network interface controller adapts the messages from the PEs to NoC routers and vice versa.
Rabab Ezz-Eldin, Magdy Ali El-Moursy, Hesham F. A. Hamed   +2 more
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Routerless Network-on-Chip

2018 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2018
Traditional bus-based interconnects are simple and easy to implement, but the scalability is greatly limited. While router-based networks-on-chip (NoCs) offer superior scalability, they also incur significant power and area overhead due to complex router structures.
Fawaz Alazemi, Arash AziziMazreah, Bella Bose, Lizhong Chen   +3 more
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2010
chip, on-chip interconnection IC.
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3D Network-on-Chip

2013
As we mentioned in Chap. 1, the number of transistors kept increasing along the past few decades. That made shrinking the chip size while maintaining high performance possible. This technology scaling has allowed Systems-on-Chip (SoCs) to grow continuously in component count and complexity, which significantly led to some very challenging problems ...
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2D Network-on-Chip

2013
Future high-performance embedded SoCs will be based on multi and manycore approaches with nano-scale technology consisting of hundreds of processing and storage elements. These new paradigms are emerging as a key design solution for today’s nano-electronics design problems.
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