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Network-on-Chip and Photonic Network-on-Chip Basic Concepts: A Survey
Journal of Electronic Testing: Theory and Applications (JETTA), 2023Bahareh Asadi +2 more
exaly +2 more sources
Proceedings of the 47th Design Automation Conference, 2010
Research on Networks on Chips (NoCs) has spanned over a decade and its results are now visible in some products. Thus the seminal idea of using networking technology to address the chip-level interconnect problem has been shown to be correct. Moreover, as technology scales down in geometry and chips scale up in complexity, NoCs become the essential ...
De Micheli G. +5 more
openaire +4 more sources
Research on Networks on Chips (NoCs) has spanned over a decade and its results are now visible in some products. Thus the seminal idea of using networking technology to address the chip-level interconnect problem has been shown to be correct. Moreover, as technology scales down in geometry and chips scale up in complexity, NoCs become the essential ...
De Micheli G. +5 more
openaire +4 more sources
2018 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2018
Traditional bus-based interconnects are simple and easy to implement, but the scalability is greatly limited. While router-based networks-on-chip (NoCs) offer superior scalability, they also incur significant power and area overhead due to complex router structures.
Fawaz Alazemi +3 more
openaire +1 more source
Traditional bus-based interconnects are simple and easy to implement, but the scalability is greatly limited. While router-based networks-on-chip (NoCs) offer superior scalability, they also incur significant power and area overhead due to complex router structures.
Fawaz Alazemi +3 more
openaire +1 more source
2007 International Symposium on System-on-Chip, 2007
In this paper, we present the sensor network-on-a-chip (SNOC) paradigm for designing robust and energy-efficient systems-on-a-chip (SOC). In this paradigm, computation in the presence of nanometer non-idealities such as process variations, leakage and noise is viewed as an estimation problem. Robust statistical signal processing theory is then employed
Girish Varatkar +3 more
openaire +1 more source
In this paper, we present the sensor network-on-a-chip (SNOC) paradigm for designing robust and energy-efficient systems-on-a-chip (SOC). In this paradigm, computation in the presence of nanometer non-idealities such as process variations, leakage and noise is viewed as an estimation problem. Robust statistical signal processing theory is then employed
Girish Varatkar +3 more
openaire +1 more source
2016 IEEE International Symposium on High Performance Computer Architecture (HPCA), 2016
With increasing core counts and higher memory demands from applications, it is imperative that networks-on-chip (NoCs) provide low-latency, power-efficient communication. Conventional NoCs tend to be over-provisioned for worst-case bandwidth demands leading to ineffective use of network resources and significant power inefficiency; average channel ...
Zimo Li +2 more
openaire +1 more source
With increasing core counts and higher memory demands from applications, it is imperative that networks-on-chip (NoCs) provide low-latency, power-efficient communication. Conventional NoCs tend to be over-provisioned for worst-case bandwidth demands leading to ineffective use of network resources and significant power inefficiency; average channel ...
Zimo Li +2 more
openaire +1 more source
Network-on-Chip for Turbo Decoders
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2016The multi-application specific instruction processor (ASIP) architecture is a promising candidate for flexible high-throughput turbo decoders. This brief proposes a network-on-chip (NoC) structure for multi-ASIP turbo decoders. The process of turbo decoding is studied, and the addressing patterns for turbo codes in long term evolution (LTE) and High ...
Yang, Qingqing +3 more
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