Results 271 to 280 of about 49,281,268 (309)

Models of Computation for Networks on Chip

Sixth International Conference on Application of Concurrency to System Design (ACSD'06), 2006
Networks on chip platforms offer the opportunity to introduce a new abstraction level that defines a set of platform services with performance and power characteristics. By making the implementation of these services entirely irrelevant for system design, an effective separation of system design from component design can be achieved.
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Networks on Chips

2008
We are witnessing a growing interest in Networks on Chips (NoC) that is related to the evolution of integrated circuit technology and to the growing requirements in performance and portability of electronic systems. Current integrated circuits contain several processing cores, and even relatively simple systems, such as cellular telephones, behave as ...
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On network-on-chip comparison

10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD 2007), 2007
Erno Salminen, Ari Kulmala, Timo D. Hämäläinen   +2 more
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Formal Methods for Networks on Chips

Fifth International Conference on Application of Concurrency to System Design (ACSD'05), 2006
Systems on a chip (SoC) are complex embedded systems consisting of many hardware and software blocks. As the complexity of SoCs grows, the focus is less on the computation, and increasingly on communication. This results in a shift from design based on platforms (design templates) to design style that is communication-centric.
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Networks on Chips

2017
Networks implemented on single integrated circuit chips are important to present and future electronic technology. Different interconnection networks suitable for networks on chips are covered including stars, buses, meshes, torii, fat trees, butterfly fat trees, and octagon topologies. The architecture of nodes and switching alternatives are discussed.
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Design Technologies for Networks on Chips

First International Symposium on Networks-on-Chip (NOCS'07), 2007
Summary form only given. Networks on chips provide structured solutions for fast and low-power interconnect, but need to be adapted to the performance and physical design requirements of the host chip. Efficient and optimal design of such networks is an error-prone, tedious and time-consuming task.
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Computer on a chip and a network of chips

Proceedings of the June 4-8, 1973, national computer conference and exposition on - AFIPS '73, 1973
The paper will first discuss the various approaches to a computer on a chip as advanced by the various semiconductor vendors and in the various R&D programs sponsored by the government. This discussion will include a description of the work being performed for the Navy who are developing the technology for a 5000--10,000 gate chip.
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F1A: Networks on chip

2017 30th IEEE International System-on-Chip Conference (SOCC), 2017
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Approximate Networks on Chip

2018 Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 2018
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ChangeSUB: A power efficient multiple network-on-chip architecture

Computers and Electrical Engineering, 2020
Meisam Abdollahi, Ahmad Khonsari
exaly