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Optical Interconnects for Network on Chip
2006 1st International Conference on Nano-Networks and Workshops, 2006This paper resumes some state-of-the-art results of research in view of the realization of optical interconnects as physical link for Network on Chip (NoC). Emphasis is given in particular to amorphous Silicon technology for its actual technological compatibility with CMOS microchips.
Scandurra A. +4 more
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Layered Switching for Networks on Chip
2007 44th ACM/IEEE Design Automation Conference, 2007We present and evaluate a novel switching mechanism called layered switching. Conceptually, the layered switching implements wormhole on top of virtual cut-through switching. To show the feasibility of layered switching, as well as to confirm its advantages, we conducted an RTL implementation study based on a canonical wormhole architecture.
Zhonghai Lu, Ming Liu 0011, Axel Jantsch
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2013 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP), 2013
On-chip wireless interconnects are being investigated for applicability on network-on-chip systems of contemporary Multiprocessor Systems-on-chip (MPSoCs). Targeting both 2D and 3D semiconductor technologies, wireless interconnects are established with multiple antennas on the same die or couplers on the layers of a 3D IC package.
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On-chip wireless interconnects are being investigated for applicability on network-on-chip systems of contemporary Multiprocessor Systems-on-chip (MPSoCs). Targeting both 2D and 3D semiconductor technologies, wireless interconnects are established with multiple antennas on the same die or couplers on the layers of a 3D IC package.
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CDMA technique for Network-on-Chip
2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2012A Code-Division Multiple Access (CDMA) based on-chip communication network is proposed in this paper. The proposed design features a novel encoding and decoding scheme for CDMA transmission which improves area, latency and power dissipation of the network on Chip (NoC).
Ahmed A. El Badry +1 more
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Power efficient Networks on Chip
2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009), 2009a low power switch design is proposed to achieve power-efficient Network on Chip (NoC). The proposed NoC switch reduces the power consumption of the Butterfly Fat Tree (BFT) architecture by 28 % as compared to the conventional BFT switch. Moreover, the power reduction technique is applied to different NoC architectures.
Mohamed A. Abd El-Ghany +3 more
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The CONNECT Network-on-Chip Generator
Computer, 2015Efficiently supporting the communication needs of systems on chip with tens to hundreds of interacting modules requires a systematic and flexible network-on-chip (NoC) infrastructure. The freely available CONNECT generator lets users quickly navigate a range of design parameters to produce tailored NoC design instances in Verilog.
Michael K. Papamichael, James C. Hoe
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2006
The design of today's semiconductor chips for various applications, such as telecommunications, poses various challenges due to the complexity of these systems. These highly complex systems-on-chips demand new approaches to connect and manage the communication between on-chip processing and storage components and networks on chips (NoCs) provide a ...
Benini, Luca +9 more
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The design of today's semiconductor chips for various applications, such as telecommunications, poses various challenges due to the complexity of these systems. These highly complex systems-on-chips demand new approaches to connect and manage the communication between on-chip processing and storage components and networks on chips (NoCs) provide a ...
Benini, Luca +9 more
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Networking on chip with platform FPGAs
Proceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT) (IEEE Cat. No.03EX798), 2004This paper is concerned with networking at the chip level. Networks on chip have become a convenient focus for discussing the architecture of systems on chip, and design methodologies for such systems. One central question for such a focus concerns the extent to which it is useful or realistic just to scale down approaches used conventionally in larger-
Gordon J. Brebner, Delon Levi
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Key Problems on Network-on-Chip
2007 10th IEEE International Conference on Computer-Aided Design and Computer Graphics, 2007Network-on-chip (NoC) has been recently proposed as a promising solution to complex system-on-chip communication problems and widely received by academe and industry. NoC involves in many problems ranging from physical layer to application layer, the paper mainly focuses on the key problems on NoC.
Youyao Liu, Yaodong Tan, Jungang Han
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2019 IEEE Symposium on High-Performance Interconnects (HOTI), 2019
Xilinx Versal Adaptable Compute Acceleration Platform (ACAP) is a new software-programmable heterogenous compute platform. The slowing of Moores law and the everpresent need for higher levels of compute performance has spurred the development of many domain specific accelerator architectures. ACAP devices are well suited to take advantage of this trend.
Ian Swarbrick +7 more
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Xilinx Versal Adaptable Compute Acceleration Platform (ACAP) is a new software-programmable heterogenous compute platform. The slowing of Moores law and the everpresent need for higher levels of compute performance has spurred the development of many domain specific accelerator architectures. ACAP devices are well suited to take advantage of this trend.
Ian Swarbrick +7 more
openaire +1 more source