Results 71 to 80 of about 11,698 (174)

Eightdirectional Smart Reconfigurable Router Design for Network on Chip (Noc)

International Journal of Engineering and Advanced Technology, 2019
Designing N.O.C routers are based on performance parameters like power dissipation , energy , latency[2] .These performance are usually defined during design time.Taking under consideration all parameters as buffer size while designing lead to higher side of power dissipation and higher latency .
Himani Mittal Gupta, Yogendera Kumar
openaire   +1 more source

Energy-Aware Network-on-Chip Application Mapping Based on Domain Knowledge Genetic Algorithm [PDF]

, 2014
This paper addresses energy-aware application mapping for large-scale Network-on-chip (NoC). The increasing number of intellectual property (IP) cores in multi-processor system-on-chips (MPSoCs) makes NoC application mapping more challenging to find ...
Andromeda, T. (Trias), Hau, Y. W. (Yuan), Marsono, M. N. (M), Shaikh-Husin, N. (N), Tei, Y. Z. (Yin)   +4 more
core  

Compromising Network-on-Chip (NoC) IPs through traffic analysis attacks

, 2022
With the evolution of multi-core processors, Network-on-Chip (NoC) was proposed as a solution for providing scalable interconnection fabric in Multiprocessor System-on-Chip (MP-SoC). As NoCs communicate with different components in SoCs, they are vulnerable to Hardware Trojan (HT) attacks.
openaire   +2 more sources

Realtime multiprocessor for mobile ad hoc networks [PDF]

Advances in Radio Science, 2008
This paper introduces a real-time Multiprocessor System-On-Chip (MPSoC) for low power wireless applications. The multiprocessor is based on eight 32bit RISC processors that are connected via an Network-On-Chip (NoC). The NoC follows a novel approach with
T. Jungeblut, M. Grünewald, M. Porrmann, U. Rückert   +3 more
doaj  

Editorial for the Special Issue on Network on Chip (NoC) and Reconfigurable Systems. [PDF]

Micromachines (Basel), 2023
Zitouni A.
europepmc   +1 more source

A Self-Adaptive Mapping Approach for Network on Chip With Low Power Consumption

IEEE Access, 2019
Application mapping of disseminated intellectual property into Network on Chip (NoC) is a well-defined NP-Hard problem. Improvement of network performance in NoC is purely based on an effective mapping approach with cost and performance metrics ...
Aravindhan Alagarsamy, Lakshminarayanan Gopalakrishnan, Sundarakannan Mahilmaran, Seok-Bum Ko   +3 more
doaj   +1 more source

Energy Efficient of Network-on- Chip (NOC) for System-on-Chip

, 2020
This material presented in 2nd ICESE 2020 Panel Session, 11th November ...
Mohd Nazri Mohd Warip, Ng Yen Phing
openaire   +1 more source

SRCPAR—Spike Response-Based Congestion Prediction for Adaptive Routing for 2D NoCs

IEEE Access
Network-on-Chip (NoC) architectures offer several advantages over bus-based systems, including improved scalability, efficient and high-performance interconnects, reduced wire routing congestion, and enhanced power efficiency.
Rajendra Singh, Manoj Kumar Bohra, Ashish Sharma, Sourabh Singh Verma, Devershi Pallavi Bhatt, Amit Kumar Bairwa, Masoud Daneshtalab   +6 more
doaj   +1 more source

Hybrid Network-on-Chip: An Application-Aware Framework for Big Data

Complexity, 2018
Burst growing IoT and cloud computing demand exascale computing systems with high performance and low power consumption to process massive amounts of data.
Juan Fang, Sitong Liu, Shijian Liu, Yanjin Cheng, Lu Yu   +4 more
doaj   +1 more source

Expansible Network-on-Chip Architecture

Advances in Electrical and Computer Engineering, 2018
Interconnection has a great importance to provide a high bandwidth communication among parallel systems. On multi-core context, Network-on-Chip is the default intra-chip interconnection choice, providing low contention and high bandwidth between the ...
PIRES, I. L. P., ALVES, M. A. Z., ALBINI, L. C. P.   +2 more
doaj   +1 more source