Results 61 to 70 of about 11,636 (194)
e-Prime: Advances in Electrical Engineering, Electronics and EnergyChip Multiprocessors (CMPs) leverage multiple processing units to improve computational speed and efficiency. Routing algorithms in NoC (Network-on-Chip) architectures ensure efficient data communication between these units, addressing challenges such as
Asrani Lit +2 more
doaj +1 more source
Tolerating Permanent Faults in the Input Port of the Network on Chip Router
Journal of Low Power Electronics and Applications, 2019 Deep submicron technologies continue to develop according to Moore’s law allowing hundreds of processing elements and memory modules to be integrated on a single chip forming multi/many-processor systems-on-chip (MPSoCs).
Hala J. Mohammed +2 more
doaj +1 more source
Design of a multicast router for network-on-chip architectures with irregular topologies [PDF]
, 2015 As chip complexity keeps increasing in system-on-chip (SoC), the on-chip interconnect has become a critical issue for large-scale chip design.It has been proposed that the packet-switched network exchanging messages between intellectual property (IP ...
Chi, Hsin-Chou +2 more
core
A DVFS Cycle Accurate Simulation Framework with Asynchronous NoC Design for Power-Performance Optimizations [PDF]
, 2015 Network-on-Chip (NoC) is a flexible and scalable solution to interconnect multi-cores, with a strong influence on the performance of the whole chip.
Fornaciari, William +2 more
core +1 more source
Power Spectra of Physics‐Based and Data‐Driven Ensembles
Meteorological Applications, Volume 32, Issue 5, September/October 2025.We plot variance spectra of ensemble analyses, forecasts, and errors to investigate the scale dependence of reliability and skill. Physics‐based and data‐driven spectra are similar at large scales, while small‐scale reliability is difficult to evaluate and achieve.
Mark J. Rodwell +4 more
wiley +1 more source
A Novel Analytical Model for Network-on-Chip using Semi-Markov Process
Advances in Electrical and Computer Engineering, 2011 Network-on-Chip (NoC) communication architecture is proposed to resolve the bottleneck of Multi-processor communication in a single chip. In this paper, a performance analytical model using Semi-Markov Process (SMP) is presented to obtain the NoC ...
WANG, J., LI, Y., PENG, Q.
doaj +1 more source
Quarc: a high-efficiency network on-chip architecture [PDF]
, 2009 The novel Quarc NoC architecture, inspired by the Spidergon scheme is introduced as a NoC architecture that is highly efficient in performing collective communication operations including broadcast and multicast.
Maji, Partha +2 more
core +1 more source
Environmental DNA, Volume 7, Issue 4, July–August 2025.Autonomous environmental DNA (eDNA) sampling technologies are transforming biodiversity monitoring by enabling high‐resolution, time‐series biological data collection as an alternative to traditional sampling methods. This review synthesizes recent advancements in aquatic autonomous eDNA instrumentation, emerging in situ analysis capabilities, and key ...
Kevan M. Yamahara +15 more
wiley +1 more source
Performance Implications of NoCs on 3D-Stacked Memories: Insights from the Hybrid Memory Cube
, 2018 Memories that exploit three-dimensional (3D)-stacking technology, which integrate memory and logic dies in a single stack, are becoming popular. These memories, such as Hybrid Memory Cube (HMC), utilize a network-on-chip (NoC) design for connecting their
Asgari, Bahar +6 more
core +1 more source
A performance model of communication in the quarc NoC [PDF]
, 2008 Networks on-chip (NoC) emerged as a promising communication medium for future MPSoC development. To serve this purpose, the NoCs have to be able to efficiently exchange all types of traffic including the collective communications at a reasonable cost ...
Moadeli, M. +2 more
core +1 more source