Results 151 to 160 of about 868 (191)
Some of the next articles are maybe not open access.
2013
As the CMOS technology nodes progress aggressively into “nano” era, introduction of High-k Metal gate (HKMG) has became key to maintain the scaling trend. Much effort has been devoted to understand the reliability aspects of HKMG over the last decade.
Kai Zhao +3 more
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As the CMOS technology nodes progress aggressively into “nano” era, introduction of High-k Metal gate (HKMG) has became key to maintain the scaling trend. Much effort has been devoted to understand the reliability aspects of HKMG over the last decade.
Kai Zhao +3 more
openaire +1 more source
SRAM-based NBTI/PBTI sensor system design
Proceedings of the 47th Design Automation Conference, 2010NBTI has been a major aging mechanism for advanced CMOS technology and PBTI is also looming as a big concern. This work first proposes a compact on-chip sensor design that tracks both NBTI and PBTI for both logic and SRAM circuits. Embedded in an SRAM array the sensor takes the form of a 6T SRAM cell and is at least 30× smaller than previous designs ...
Zhenyu Qi 0001 +6 more
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2013
Interaction of different materials in the multilayer high-k/metal gate stacks results in the formation of structural defects in the high-k dielectric and interfacial SiO2 layer. This section discusses the impact that defects in intrinsic Hf-based dielectric layers have on the electron trapping process and concurrent defect generation occurring under ...
Chadwin D. Young, Gennadi Bersuker
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Interaction of different materials in the multilayer high-k/metal gate stacks results in the formation of structural defects in the high-k dielectric and interfacial SiO2 layer. This section discusses the impact that defects in intrinsic Hf-based dielectric layers have on the electron trapping process and concurrent defect generation occurring under ...
Chadwin D. Young, Gennadi Bersuker
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Study PBTI and NBTI of GAA-MNC TFTs
2010 5th International Microsystems Packaging Assembly and Circuits Technology Conference, 2010GAA-MNC TFT shows higher on-current, higher mobility, steeper subthreshold swing and lower threshold voltage than CP TFT. In this letter, we study in view of PBTI and NBTI of GAA-MNC TFT. Under room temperature, the PBTI or NBTI of GAA-MNC TFT show more serious degradation than CP TFT.
Tsung-Kuei Kang +5 more
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PBTI Study in Native High Voltage Device
2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA), 2019The native HV device (w/o Vt implantation) and regular HV device (w/i Vt implantation) of PBTI Vt shift behaviors are investigated in this paper, and an envisioned mechanism is provided. Native HV device showed a high Vt shift at the beginning of Vg stress, the Ig-Vg curve measured supported this observation; also, the mismatch characterizations were ...
B. A. Tsai +4 more
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Modeling of HKMG Stack Process Impact on Gate Leakage, SILC and PBTI
2021 IEEE International Reliability Physics Symposium (IRPS), 2021Gate stack process (pre-clean, IL, IL/HK interface, HK, post-HK Nitridation) impact on gate leakage, SILC and PBTI is analyzed. IL and HK thickness, channel/IL and IL/HK energy-barrier offsets impact on gate leakage and SILC response from generated bulk traps inside IL and HK is quantified.
Dimple Vijay Kochar +3 more
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Impacts of NBTI/PBTI on power gated SRAM
Journal of Central South University, 2013A signal probability and activity probability (SPAP) model was proposed firstly, to estimate the impacts of the negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) on power gated static random access memory (SRAM).
Ping Huang, Zuo-cheng Xing
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A Novel Insight of pBTI Degradation in GaN-on-Si E-Mode MOSc-HEMT
, 2018 International audienceFor the first time, ultrafast AC pBTI measurements are applied to GaN on Si E-mode MOSc-HEMT and compared to DC pBTI. Full recess Al$_2$ O$_3$ /GaN MOS gate is submitted to AC signals with various frequencies, duty factors and ...
Xavier Garros +2 more
exaly +2 more sources
Investigation of NBTI and PBTI induced aging in different LUT implementations
2011 International Conference on Field-Programmable Technology, 2011Transistor aging mostly due to Negative and Positive Bias Temperature Instability (NBTI and PBTI) is a major reliability threat for VLSI circuits fabricated in nanometer technology nodes. These phenomena can shift the threshold voltage of transistor over time, increase their delays and cause timing failure and ultimately reduction of lifetime of VLSI ...
Kiamehr, S., Amouri, A., Tahoori, M. B.
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A Low Area Overhead NBTI/PBTI Sensor for SRAM Memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017Bias temperature instability (BTI) is known as one serious reliability concern in nanoscale technologies. BTI gradually increases the absolute value of threshold voltage ( $V_{\mathrm{ th}}$ ) of MOS transistors. The main consequence of $V_{\mathrm{ th}}$ shift of the SRAM cell transistors is the static noise margin (SNM) degradation. The SNM
Maryam Karimi +2 more
openaire +2 more sources