Results 161 to 170 of about 868 (191)
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Impact of NBTI/ HCI /PBTI ON 6T SRAM reliability
2020 Fourth World Conference on Smart Trends in Systems, Security and Sustainability (WorldS4), 2020The main focus of this article is the reliability and aging of the 6T (SRAM) Static random access memories. From many days of the SRAM circuit have been used, so consider its reliability and aging factor. In this paper reliability and aging are performed under the parameters of (HCI), (NBTI) and (PBTI).
Vartika Pandey +2 more
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On-chip circuit to monitor long-term NBTI and PBTI degradation
Microelectronics Reliability, 2013Abstract A circuit for on-chip monitoring bias-temperature instability (BTI) degradation of CMOS devices, which distinguishes between NBTI and PBTI, is described. Intended for long-term monitoring of field-installed systems, the measurements are performed entirely on chip, and reported through digital scan chains.
Keith A. Jenkins, Pong-Fei Lu
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Investigation of The NBTI and PBTI Effects on Multiplexer Circuit Performances
2020 IEEE International Conference on Semiconductor Electronics (ICSE), 2020This paper investigates the effects of Negative Bias Temperature Instability (NBTI) & Positive Bias Temperature Instability (PBTI) on 2-to-1 multiplexer circuit performances. The key objective of this research is to analyse the effects of NBTI and PBTI on the delay and average power of 2-to-1 multiplexer circuit.
M. S. S. Mohamad Saofi +3 more
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Concurrent PBTI and hot carrier degradation in n-channel MuGFETs
Microelectronics Reliability, 2011Abstract The experimental investigations on the concurrent PBTI and CHC degradation in n-channel MuGFETs have been performed with different stress gate voltages, gate lengths, fin widths, and side surface orientations of fin body. The observed results suggest that the enhanced hot carrier degradation at elevated temperature is due to the interaction ...
Seung Min Lee +3 more
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Process-Dependent N/PBTI Characteristics of TiN Gate FinFETs
IEEE Electron Device Letters, 2012A study of the negative and positive bias temperature instability (N/PBTI) reliability of FinFETs with different TiN metal gates deposited by either atomic layer deposition (ALD) or physical vapor deposition (PVD) on HfO2 dielectrics found that the nonuniformity of the interfacial oxide layer is closely related to reliability characteristics.
Young Gon Lee +2 more
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On the PBTI degradation of pMOSFETs and its impact on IC lifetime
2011 IEEE International Integrated Reliability Workshop Final Report, 2011Negative Bias Temperature Instability (NBTI) of pMOSFETs is nowadays the most prominent device degradation mechanism reported in the literature and a limiting factor for CMOS technology scaling. In contrast, for Positive Bias Temperature Instability (PBTI) of pMOSFET only very few publications can be found [1–4].
Christian Schlunder +3 more
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Reliability Analysis of Comparator: NBTI, PBTI, HCI, AGEING
2018In this research, we focus on analytical reliability assessment. The reliability of meticulous conditions of voltage, temperature and degradation will be reported to device bounds. Such as the same effect on analogue or digital device performance like Comparator cell and combined circuits.
Seelam V. Sai Viswanada Prabhu Deva Kumar +1 more
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Impact of gate poly doping and oxide thickness on the N- and PBTI in MOSFETs
Microelectronics Reliability, 2011Abstract We study n- and pMOS devices with 3.2–30 nm thick SiON or SiO2 gate dielectrics and n++ or p++ doped polysilicon gates to identify the type and energetic location of defects created through bias temperature stress. The results clearly indicate a dependence of the type of BTS induced defects on the stress polarity and the gate poly doping. If
Gregor Pobegen +3 more
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Aging-aware timing analysis considering combined effects of NBTI and PBTI
International Symposium on Quality Electronic Design (ISQED), 2013Transistor aging due to Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI) is one of the major reliability issues of VLSI circuits fabricated at nanometer technology nodes. Transistor aging increases the circuit delay over the time and ultimately leads to lifetime reduction of VLSI chips.
Kiamehr, S., Firouzi, F., Tahoori, M. B.
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Investigating the impact of the defect dynamic characteristics on the PBTI in the high-κ gate device
Microelectronics Reliability, 2018Abstract Recent device reliability studies on the metal/high-κ device observed the inter-convertible characteristics of the electron trap levels between the shallow and deep defect states under cyclic positive-bias temperature stressing. Although the oxygen vacancy and oxygen interstitial defect, being two typical types of defects in the high-κ oxide,
Xianqiang Liu +6 more
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