Results 51 to 60 of about 868 (191)
In this paper, various D flip‐flops (FFs) (DFFs) are studied and analyzed based on the performance and reliability effects of different architectures, technology, area, power, delay, and several other key performance parameters of DFFs. Based on these parameters, a few selected DFFs such as C2SFF, conditional‐bridging FF (CBFF)‐S, self‐shut‐off pulsed ...
Syeda Hurmath Juveria +5 more
wiley +1 more source
Beyond Flexible: Unveiling the Next Era of Flexible Electronic Systems
Flexible electronics are essential in various fields like wearables, healthcare, and environmental sensing due to their flexibility, lightweight construction, and low profile. These systems conform to diverse surfaces, enhancing or replacing bulky instruments in many applications.
Min Sung Kim +14 more
wiley +1 more source
In this letter, we present a comparative study of positive bias temperature instability (PBTI) reliability in InxGa1-xAs FinFET with varying Indium (x = 0.53, 0.70) percentage and quantization [bulk, quantum well (QW)].
DATTA, S +7 more
core +1 more source
Study on the difference between ID(VG) and C(VG) pBTI shifts in GaN-on-Si E-mode MOSc-HEMT
International audienceIn this study, we investigate the difference between ID(VG) and C(VG) pBTI shifts on GaN-on-Si E-mode MOS-channel HEMTs, under various gate voltage stresses (VGStress) and temperatures (T).
A.G. Viey +31 more
core +2 more sources
Analysis and EOT Scaling on Top‐ and Double‐Gate 2D CVD‐Grown Monolayer MoS2 FETs
This study investigates double‐gate chemical vapor deposition (CVD)‐grown monolayer molybdenum disulfide (1L‐MoS2) field‐effect‐transistors (FETs) and elucidates the mechanisms for improvements compared to single top‐gated devices. It also reports on the impact of equivalent oxide thickness (EOT) scaling on subthreshold swing (SS) and gate hysteresis ...
Naim Hossain Patoary +4 more
wiley +1 more source
PBTI in HKMG nMOS Transistors-Effect of Width, Layout, and Other Technological Parameters
This paper discusses in detail the effects of transistor width, layout, and technological parameters like gate dielectric and Lanthanum capping layer thickness on positive bias temperature instability (PBTI) of nMOS transistors fabricated using 28-nm ...
RAO, VR +5 more
core +1 more source
Threshold voltage instability of SiC MOSFETs under very‐high temperature and wide gate bias
This article presents a detailed investigation of the threshold voltage degradation of commercial SiC MOSFETs due to the application of high temperature and DC bias stress in a more comprehensive voltage range and a higher temperature range. Abstract Threshold voltage (VTH) instability affects the reliability of silicon carbide (SiC) MOSFETs.
Cong Chen +3 more
wiley +1 more source
We present reliability analysis of the two most critical interfaces in III-V Heterojunction Tunnel FET (HTFET) design: (1) Tunnel Heterojunction is characterized in three-dimensional atomic scale resolution using Atom Probe Tomography.
K. Henry +25 more
core +1 more source
This summary diagram comprehensively and reasonably reviews the evolution of BDT‐based donor materials over the last 20 years by subdividing the molecular design strategies of main‐chain engineering, side‐chain engineering as well as other engineering based on the detailed molecular structure of BDT‐based polymer donors and small molecule donors ...
Congqi Lin +3 more
wiley +1 more source
This work presents GaN-on-Si metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs) featuring a quaternary InAlGaN barrier and gate field plate (GFP) for power device applications.
Shivendra Kr. Rathaur +4 more
doaj +1 more source

