Results 71 to 80 of about 102 (93)
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A Charge-Trapping Model for the Fast Component of Positive Bias Temperature Instability (PBTI) in High-$\kappa $ Gate-Stacks

IEEE Transactions on Electron Devices, 2014
We propose a physical model for the fast component ( \( s) of the positive bias temperature instability (PBTI) process in SiO x /HfO2 gate-stacks. The model is based on the electron-phonon interaction governing the trapping/emission of injected electrons at the preexisting defects in the dielectric stack.
VANDELLI, LUCA   +5 more
openaire   +2 more sources

nTunnel FET (nTFET) Reliability Study Against Positive Bias Temperature Instability (PBTI) for Different Device Architectures

2020
In this paper, for the first time, the nTFET reliability and stability have been studied against the adverse effect of positive bias temperature instability (PBTI) for three different device architectures, viz. elevated drain-(ED-), elevated source-(ES-) and elevated source–drain-(ESD-) TFETs, in terms of threshold voltage (VT) shift, on-current/off ...
Suman Das   +2 more
openaire   +1 more source

Positive Bias Temperature Instability (PBTI) Characteristics of Contact-Etch-Stop-Layer-Induced Local-Tensile-Strained $\hbox{HfO}_{2}$ nMOSFET

IEEE Electron Device Letters, 2008
The positive bias temperature instability (PBTI) characteristics of contact-etch-stop-layer (CESL)-strained HfO2 nMOSFET are thoroughly investigated. For the first time, the effects of CESL on an HfO2 dielectric are investigated for PBTI characteristics.
Woei-Cherng Wu   +6 more
openaire   +1 more source

Understanding lifetime prediction methodology for In0.53Ga0.47As nFETs under Positive Bias Temperature Instability (PBTI) condition

2019 IEEE 26th International Symposium on Physical and Failure Analysis of Integrated Circuits (IPFA), 2019
In 0.53 Ga 0.47 As as a high mobility channel material is a strong candidate for nFETs, which, however, suffers severe PBTI reliability. In this work, we show the failure of conventional method for its lifetime prediction and demonstrate the required paradigm shift in characterizing such technology. Then a comprehensive investigation on PBTI is carried
Zhigang Ji, Xiong Zhang, Jianfu Zhang
openaire   +1 more source

Influence of ultra-thin TiN thickness (1.4 nm and 2.4 nm) on positive bias temperature instability (PBTI) of high- k /metal gate nMOSFETs with gate-last process

Chinese Physics B, 2015
The positive bias temperature instability (PBTI) degradations of high-k/metal gate (HK/MG) nMOSFETs with thin TiN capping layers (1.4 nm and 2.4 nm) are systemically investigated. In this paper, the trap energy distribution in gate stack during PBTI stress is extracted by using ramped recovery stress, and the temperature dependences of PBTI (90 °C, 125
Lu-Wei Qi   +13 more
openaire   +1 more source

Systematic Study on Positive Bias Temperature Instability(PBTI) of ZrO2-based Ge nMOSFETs with Interlayer Passivations

2022 International Conference on IC Design and Technology (ICICDT), 2022
Lulu Chou   +5 more
openaire   +1 more source

Positive Bias Temperature Instability of SiC-MOSFETs Induced by Switching Operation (AC-PBTI)

Extended Abstracts of the 2016 International Conference on Solid State Devices and Materials, 2016
E. Murakami   +3 more
openaire   +1 more source

nTunnel FET (nTFET) Reliability Study Against Positive Bias Temperature Instability (PBTI) for Different Device Architectures

Lecture Notes in Electrical Engineering, 2021
Suman Das   +2 more
exaly  

Lateral profiling of gate dielectric damage by off-state stress and positive-bias temperature instability

Microelectronics Reliability, 2021
Yang-Kyu Choi   +2 more
exaly  

Positive Bias Temperature Instability (PBTI) in n- and p-Channel Polysilicon Thin-Film Transistors (TFTs) for High-Voltage Applications

Solid-State Electronics
B. Kaczer   +9 more
openaire   +1 more source

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