Results 21 to 30 of about 22,912 (307)

Investigation of the RISC-V

Proceedings of the Institute for System Programming of the RAS, 2020
Vladimir Alexandrovitch Frolov, Vladimir Alexandrovitch Galaktionov, Vadim Vladimirovitch Sangarov   +2 more
openaire   +3 more sources

Holistic RISC-V Virtualization

Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023
This work describes our efforts to provide a holistic hardware RISC-V virtualization SoC based on the CVA6 core. At the core level, we implemented hardware support for virtualization through the ratified Hypervisor instruction set architecture (ISA) extension version 1.0.
Bruno Sá, Francisco Marques, Manuel Rodriguez, José Martins, Sandro Pinto   +4 more
openaire   +2 more sources

Computer Engineering Education Experiences with RISC-V Architectures—From Computer Architecture to Microcontrollers

Journal of Low Power Electronics and Applications, 2022
With the growing popularity of RISC-V and various open-source released RISC-V processors, it is now possible for computer engineers students to explore this simple and relevant architecture, and also, these students can explore and design a ...
Peter Jamieson, Huan Le, Nathan Martin, Tyler McGrew, Yicheng Qian, Eric Schonauer, Alan Ehret, Michel A. Kinsy   +7 more
doaj   +1 more source

Design and Implementation of a 256-Bit RISC-V-Based Dynamically Scheduled Very Long Instruction Word on FPGA

IEEE Access, 2020
This study describes the design and implementation of a 256-bit very long instruction word (VLIW) microprocessor based on the new RISC-V instruction set architecture (ISA).
Nguyen My Qui, Chang Hong Lin, Poki Chen
doaj   +1 more source

Backporting RISC-V Vector Assembly

, 2023
Leveraging vectorisation, the ability for a CPU to apply operations to multiple elements of data concurrently, is critical for high performance workloads. However, at the time of writing, commercially available physical RISC-V hardware that provides the RISC-V vector extension (RVV) only supports version 0.7.1, which is incompatible with the latest ...
Joseph K. L. Lee, Maurice Jamieson, Nick Brown   +2 more
openaire   +2 more sources

An Energy-Efficient Reconfigurable DTLS Cryptographic Engine for End-to-End Security in IoT Applications [PDF]

, 1957
This paper presents a reconfigurable cryptographic engine that implements the DTLS protocol to enable end-to-end security for IoT. This implementation of the DTLS engine demonstrates 10x reduction in code size and 438x improvement in energy-efficiency ...
Banerjee, Utsav, Juvekar, Chiraag, Wright, Andrew, Arvind, Chandrakasan, Anantha P.   +4 more
core   +6 more sources

Symmetric Cryptography on RISC-V: Performance Evaluation of Standardized Algorithms

Cryptography, 2022
The ever-increasing need for securing computing systems using cryptographic algorithms is spurring interest in the efficient implementation of common algorithms.
Görkem Nişancı, Paul G. Flikkema, Tolga Yalçın   +2 more
doaj   +1 more source

A Unified PUF and Crypto Core Exploiting the Metastability in Latches

Future Internet, 2022
Hardware acceleration of cryptography algorithms represents an emerging approach to obtain benefits in terms of speed and side-channel resistance compared to software implementations.
Ronaldo Serrano, Ckristian Duran, Marco Sarmiento, Tuan-Kiet Dang, Trong-Thuc Hoang, Cong-Kha Pham   +5 more
doaj   +1 more source

Advanced Embedded System Modeling and Simulation in an Open Source RISC-V Virtual Prototype

Journal of Low Power Electronics and Applications, 2022
RISC-V is a modern Instruction Set Architecture (ISA) that, by its open nature in combination with a clean and modular design, has enormous potential to become a game changer in the Internet of Things (IoT) era. Recently, SystemC-based Virtual Prototypes
Pascal Pieper, Vladimir Herdt, Rolf Drechsler   +2 more
doaj   +1 more source

Design of SoC System for Convolution Acceleration Based on RISC-V Processor [PDF]

Jisuanji gongcheng, 2021
To improve the computation and energy efficiency of Convolutional Neural Network(CNN),this paper proposes a convolution accelerator with 8 bit fixed-point data as input.The accelerator supports common CNN calculations,including activation,Batch ...
ZHANG Kunning, ZHAO Shuo, HE Hu, DENG Ning, YANG Xu
doaj   +1 more source