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ECC Memory for Fault Tolerant RISC-V Processors [PDF]
Architecture of Computing Systems – ARCS 202033rd International Conference, 2020 Numerous processor cores based on the popular RISC-V Instruction Set Architecture have been developed in the past few years and are freely available. The same applies for RISC-V ecosystems that allow to implement System-on-Chips with RISC-V processors on
Dörflinger A +5 more
europepmc +3 more sources
A Survey of the RISC-V Architecture Software Support
IEEE Access, 2022 RISC-V is a novel open instruction set architecture that supports multiple platforms while maintaining simplicity and reliability. Despite its novelty, the software support for RISC-V has been increasing in the last years, given that popular toolchains ...
Benjamin W. Mezger +4 more
doaj +1 more source
Developing a Multicore Platform Utilizing Open RISC-V Cores
IEEE Access, 2021 RISC-V has been experiencing explosive growth since its first appearance in 2011. Dozens of free and open cores developed based on this instruction set architecture have been released, and RISC-V based devices optimized for specific applications such as ...
Hyeonguk Jang +6 more
doaj +1 more source
Is RISC-V ready for Space? A Security Perspective
2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2022 Integrated circuits employed in space applications generally have very low-volume production and high performance requirements. Therefore, the adoption of Commercial-Off-The-Shelf (COTS) components and Third Party Intellectual Property cores (3PIPs) is of extreme interest to make system design, implementation and deployment cost-effective and viable w ...
Luca Cassano +6 more
openalex +5 more sources
Return-Oriented Programming on RISC-V [PDF]
Proceedings of the 15th ACM Asia Conference on Computer and Communications Security, 2020 This paper provides the first analysis on the feasibility of Return-Oriented Programming (ROP) on RISC-V, a new instruction set architecture targeting embedded systems. We show the existence of a new class of gadgets, using several Linear Code Sequences And Jumps (LCSAJ), undetected by current Galileo-based ROP gadget searching tools.
Jaloyan, Georges-Axel +5 more
openaire +2 more sources
IEEE Access, 2021 A trusted execution environment (TEE) is a new hardware security feature that is isolated from a normal OS (i.e., rich execution environment (REE)). The TEE enables us to run a critical process, but the behavior is invisible from the normal OS, which ...
Kuniyasu Suzaki +3 more
doaj +1 more source
Test-driving RISC-V Vector hardware for HPC [PDF]
ISC Workshops, 2023 Whilst the RISC-V Vector extension (RVV) has been ratified, at the time of writing both hardware implementations and open source software support are still limited for vectorisation on RISC-V.
Joseph Lee +3 more
semanticscholar +1 more source
LLVM RISC-V RV32X Graphics Extension Support and Characteristics Analysis of Graphics Programs
IEEE Access, 2023 In recent years, virtual reality technology has become the dominant means of human-computer interaction, with computer graphics rendering technology being a crucial component in realizing virtual reality experiences.
Peng Wang, Zhi-Bin Yu
doaj +1 more source
Journal of Low Power Electronics and Applications, 2022 With the growing popularity of RISC-V and various open-source released RISC-V processors, it is now possible for computer engineers students to explore this simple and relevant architecture, and also, these students can explore and design a ...
Peter Jamieson +7 more
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A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors [PDF]
, 2023 With the continued success of the open RISC-V architecture, practical deployment of RISC-V processors necessitates an in-depth consideration of their testability, safety and security aspects.
Abolfazl Sajadi +19 more
core +1 more source