Results 21 to 30 of about 21,625 (285)
Is RISC-V ready for Space? A Security Perspective
2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2022 Integrated circuits employed in space applications generally have very low-volume production and high performance requirements. Therefore, the adoption of Commercial-Off-The-Shelf (COTS) components and Third Party Intellectual Property cores (3PIPs) is of extreme interest to make system design, implementation and deployment cost-effective and viable w ...
Cassano L. +6 more
openaire +5 more sources
Low-Power Magnetic Displacement Sensor Based on RISC-V Embedded System [PDF]
SensorsWith the emergence of RISC-V architecture in embedded devices, its inherent low-power features have propelled its extensive adoption across various industrial settings.
Tao Sun, Yue Song, Huiyun Yang
doaj +2 more sources
Return-Oriented Programming in RISC-V
, 2020 RISC-V is an open-source hardware ISA based on the RISC design principles, and has been the subject of some novel ROP mitigation technique proposals due to its open-source nature. However, very little work has actually evaluated whether such an attack is feasible assuming a typical RISC-V implementation.
Gu, Garrett, Shacham, Hovav
openaire +4 more sources
Functional Verification of a RISC-V Vector Accelerator [PDF]
IEEE Design & Test, 2023 We present the functional verification efforts for an academic RISC-V based vector accelerator, successfully taped-out in the context of the European Processor Initiative. For our novel RISC-V based decoupled vector accelerator, we built a verification infrastructure consisting of a UVM environment, performing step by step co-simulation of all vector ...
Victor Jimenez +11 more
openaire +5 more sources
A Survey on RISC-V-Based Machine Learning Ecosystem
Information (Switzerland), 2023 In recent years, the advancements in specialized hardware architectures have supported the industry and the research community to address the computation power needed for more enhanced and compute intensive artificial intelligence (AI) algorithms and ...
Stavros Kalapothas +2 more
exaly +3 more sources
A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC–DC Converters in 28 nm FDSOI [PDF]
IEEE Journal of Solid-State Circuits, 2016 This work demonstrates a RISC-V vector microprocessor implemented in 28 nm FDSOI with fully integrated simultaneous-switching switched-capacitor DC-DC (SC DC-DC) converters and adaptive clocking that generates four on-chip voltages between 0.45 and 1 V ...
Brian Zimmer +2 more
exaly +3 more sources
A RISC-V SystemC-TLM simulator [PDF]
, 2020 This work presents a SystemC-TLM based simulator for a RISC-V microcontroller. This simulator is focused on simplicity and easy expandable of a RISC-V. It is built around a full RISC-V instruction set simulator that supports full RISC-V ISA and extensions M, A, C, Zicsr and Zifencei.
Màrius
+5 more sources
Epileptic Seizure Detection on an Ultra-Low-Power Embedded RISC-V Processor Using a Convolutional Neural Network [PDF]
Biosensors, 2021 Andreas Bahr, Peer Wulff, Th Strunskus
exaly +2 more sources
ISA semantics for ARMv8-a, RISC-v, and CHERI-MIPS [PDF]
Proceedings of the ACM on Programming Languages, 2019 Architecture specifications notionally define the fundamental interface between hardware and software: the envelope of allowed behaviour for processor implementations, and the basic assumptions for software development and verification. But in practice, they are typically prose and pseudocode documents, not rigorous or executable artifacts, leaving ...
Brian Campbell +2 more
exaly +3 more sources
A Heterogeneous RISC-V Processor for Efficient DNN Application in Smart Sensing System. [PDF]
Sensors (Basel), 2021 Zhang H +7 more
europepmc +3 more sources