Results 161 to 170 of about 10,455 (213)
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Designs and analysis of non-volatile memory cells for single event upset (SEU) tolerance
2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2014This paper proposes a comprehensive approach to the designs of low-power non-volatile (NV) memory cells and for attaining Single Event Upset (SEU) tolerance. Three low-power hardened NVSRAM cell designs are proposed; these designs increase the critical charge and decrease power consumption by providing a positive (virtual) ground level voltage ...
Wei Wei +2 more
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IEEE Transactions on Nuclear Science, 2004
We present a design technique for hardening combinational circuits mapped onto Xilinx Virtex FPGAs against single-event upsets (SEUs). The signal probabilities of the lines can be used to detect SEU sensitive subcircuits of a given combinational circuit.
P.K. Samudrala, J. Ramos, S. Katkoori
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We present a design technique for hardening combinational circuits mapped onto Xilinx Virtex FPGAs against single-event upsets (SEUs). The signal probabilities of the lines can be used to detect SEU sensitive subcircuits of a given combinational circuit.
P.K. Samudrala, J. Ramos, S. Katkoori
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Techniques of Microprocessor Testing and SEU (Single Event Upset)-Rate Prediction.
1986Abstract : Several different approaches have been used in the past to assess the vulnerability of microprocessors to SEU. In this report we discuss the advantages and disadvantages of each of these test methods, and address the question of how the microprocessor test results can be used to estimate upset rate in space. Finally, as an application of the
Michael T. Marra +2 more
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Design of a novel 12T radiation hardened memory cell tolerant to single event upsets (SEU)
2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM), 2017A novel radiation hardened 12T memory cell (RH-12T) is proposed to address single event upset (SEU) problems in 65nm CMOS technology. It eliminates the possibility of a sensitive “0” storage node upset by surrounding the output nodes with NMOS, realizing a full resistance for any single node upset. Furthermore, less sensitive node pairs are obtained in
Chunyan Hu, Suge Yue, Shijin Lu
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Ion beam induced charge collection (IBICC) microscopy of ICs: relation to single event upsets (SEU)
Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with Materials and Atoms, 1993Abstract Single event upset (SEU) imaging is a new diagnostic technique recently developed using Sandia's nuclear microprobe. This technique directly images, with micron resolution, those regions within an integrated circuit which are susceptible to ion-induced malfunctions. Such malfunctions are an increasing threat to space-based systems which make
K.M. Horn +6 more
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Recent Trends in Parts SEU (Single Event Upset) Susceptibility from Heavy Ions.
1988Abstract : JPL and Aerospace have collected an extensive set of heavy ion single event upset (SEU) test data since their joint publication in December 1985. This report presented trends in SEU susceptibility for state-of-the-art parts. An ongoing single event upset (SEU) program at JPL and the Aerospace Corporation is continuing in order to assess ...
W. A. Kolasinski +4 more
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Analysis and Evaluation of the Effects of Single Event Upsets (SEU s) on Memories in Polar Decoders
2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2021Polar codes are used in 5G system for the transmission of control channels due to its excellent error correction capability for short sequence, and CRC assistant successive cancellation list (CA-SCL) decoders are commonly used in practical system. When applied in critical environment, e.g. space platform, the memories in the hardware polar decoder will
Zhen Gao +3 more
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Measurement, 2014
Abstract Commercial-Off-The-Shelf (COTS) Field Programmable Gate Array (FPGA) is becoming of increase interest in many field of high-tech applications for the possibility to implement low-cost solutions with simplicity and flexibility. Nevertheless, the presence of high energy incident particles (electrons, neutrons, protons and so on) can compromise
CIANI, LORENZO, CATELANI, MARCANTONIO
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Abstract Commercial-Off-The-Shelf (COTS) Field Programmable Gate Array (FPGA) is becoming of increase interest in many field of high-tech applications for the possibility to implement low-cost solutions with simplicity and flexibility. Nevertheless, the presence of high energy incident particles (electrons, neutrons, protons and so on) can compromise
CIANI, LORENZO, CATELANI, MARCANTONIO
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Effects of voltage stress on the single event upset (SEU) response of 65 nm flip flop
Microelectronics Reliability, 2016Abstract A newly integrated pulsed laser system has been utilized to investigate the effects of voltage stress on single event upset (SEU) of flip flop chain manufactured in 65 nm bulk CMOS technology. Laser mappings of the flip flop chain revealed that the SEU sensitive regions increased with laser energy.
C.T. Chua +4 more
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Empirical Modeling of Single-Event Upset (SEU) in NMOS Depletion-Mode-Load Static RAM (SRAM) Chips
IEEE Transactions on Nuclear Science, 1986A detailed experimental investigation of single-event upset (SEU) in static RAM (SRAM) chips fabricated using a family of high-performance NMOS (HMOS) depletion-mode-load process technologies, has been done. Empirical SEU models have been developed with the aid of heavy-ion data obtained with a three-stage tandem van de Graaff accelerator.
J. A. Zoutendyk +5 more
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