Results 141 to 150 of about 264 (165)

Recent Trends in Parts SEU (Single Event Upset) Susceptibility from Heavy Ions.

1988
Abstract : JPL and Aerospace have collected an extensive set of heavy ion single event upset (SEU) test data since their joint publication in December 1985. This report presented trends in SEU susceptibility for state-of-the-art parts. An ongoing single event upset (SEU) program at JPL and the Aerospace Corporation is continuing in order to assess ...
W. A. Kolasinski, R. Koga, W. E. Price, L. S. Smith, D. K. Nichols   +4 more
openaire   +1 more source

Notice of Violation of IEEE Publication Principles: Selective Triple Modular Redundancy for Single Event Upset (SEU) Mitigation

2009 NASA/ESA Conference on Adaptive Hardware and Systems, 2009
This paper represents a design technique for hardening circuits mapped onto FPGAs. An effective and simple algorithm for signal probabilities has been used to detect SEU (single event upset) sensitive gates for a given circuit. The circuit can be hardened against radiation effects by applying triple modular redundancy (TMR) technique to only these ...
Xiaoxuan She, P.K. Samudrala
openaire   +1 more source

Single-Event Upset (SEU) Model Verification and Threshold Determination Using Heavy Ions in a Bipolar Static RAM

IEEE Transactions on Nuclear Science, 1985
Single-Event Upset (SEU) response of a bipolar low-power Schottky-diode-clamped TTL static RAM has been observed using Br ions in the 100-240 MeV energy range and 0 ions in the 20-100 MeV range. These data complete the experimental verification of circuit-simulation SEU modeling for this device.
J. A. Zoutendyk, L. S. Smith, G. A. Soli, P. Thieberger, H. E. Wegner   +4 more
openaire   +1 more source

Experimental Evidence for a New Single-Event Upset (SEU) Mode in a CMOS SRAM Obtained from Model Verification

IEEE Transactions on Nuclear Science, 1987
Modeling of SEU has been done in a CMOS static RAM containing one-micron channel-length transistors fabricated from a P-well epilayer process using both circuit-and numerical-simulation techniques. The modeling results have been experimentally verified with the aid of heavy-ion beams obtained from a three-stage tandem van de Graaff accelerator ...
J. A. Zoutendyk, L. S. Smith, G. A. Soli, R. Y. Lo   +3 more
openaire   +1 more source

Single event upset (SEU): Diagnostic and error correction system for avioncs device

2009
In aerospace applications, Commercial-Off-The-Shelf (COTS) Field programmable Gate Array (FPGA) is becoming increasingly attractive by offering low-cost solutions, simplicity and flexibility. This research faces the problem of disturbance induced by high energy particles on electronic devices.
CIANI, LORENZO, CATELANI, MARCANTONIO, L. Veltroni   +2 more
openaire   +1 more source

Diagnostic and error correction system for avionics devices in presence of single event upset (SEU)

2013
In aerospace applications, Commercial-Off-The-Shelf (COTS) Field programmable Gate Array (FPGA) is becoming increasingly attractive by offering low-cost solutions, simplicity and flexibility. This research faces the problem of disturbance induced by high energy particles on electronic devices.
CATELANI, MARCANTONIO, CIANI, LORENZO
openaire   +1 more source

Efficient protection of polar decoders against Single Event Upsets (SEUs) on user memories

Microelectronics Reliability, 2023
Dong Tian, Zhen Gao, Ruize Wang, Qiang Liu, Anees Ullah, Pedro Reviriego   +5 more
openaire   +1 more source

Model-Based Analysis of Single-Event Upset (SEU) Vulnerability of 6T SRAM Using FinFET Technologies

2022 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2022
Semiu A. Olowogemo, Hao Qiu, Bor-Tyng Lin, William H. Robinson, Daniel B. Limbrick   +4 more
openaire   +1 more source

Critical Charge Dependency of Single Event Upset (SEU) on the Supply Voltage in Nanometric CMOS SRAMs

2022 Iranian International Conference on Microelectronics (IICM), 2022
Masume Soleimaninia, Gholamreza Raisali, Amir Moslehi   +2 more
openaire   +1 more source

Single Event Latchup (SEL) and Single Event Upset (SEU) Evaluation of Xilinx 7nm Versal™ ACAP programmable logic (PL)

2021 IEEE Nuclear and Space Radiation Effects Conference (NSREC), 2021
Pierre Maillard, Yanran P. Chen, Jeff Barton, Martin L. Voogel   +3 more
openaire   +1 more source