Results 121 to 130 of about 264 (165)

Effects of voltage stress on the single event upset (SEU) response of 65 nm flip flop

Microelectronics Reliability, 2016
Abstract A newly integrated pulsed laser system has been utilized to investigate the effects of voltage stress on single event upset (SEU) of flip flop chain manufactured in 65 nm bulk CMOS technology. Laser mappings of the flip flop chain revealed that the SEU sensitive regions increased with laser energy.
P Perdu, K Sanchez, C L Gan
exaly   +2 more sources

The Single Event Upset (SEU) Response to 590 MeV Protons

IEEE Transactions on Nuclear Science, 1984
A recent test of ten device types exposed to 590 MeV protons at SINR (Swiss Institute of Nuclear Research, Villigen) is presented to clarify the picture of SEU response to higher energy protons, such as those found in galactic cosmic rays, solar flares and trapped radiation belts.
D. K. Nichols, W. E. Price, L. S. Smith, G. A. Soli   +3 more
openaire   +1 more source

Investigation of single-event upset (SEU) in an advanced bipolar process

IEEE Transactions on Nuclear Science, 1988
An extensive analytical and experimental study of SEU in an advanced silicon bipolar process was made. The modeling used process and device parameters to model the SEU charge, collection, and circuit response derived from a special version of PISCES in cylindrical coordinates and SPICE, respectively. Data are reported for test cells of various sizes. >
J.A. Zoutendyk, E.C. Secrest, D.F. Berndt   +2 more
openaire   +1 more source

Single event upset (SEU) sensitivity dependence of linear integrated circuits (ICs) on bias conditions

IEEE Transactions on Nuclear Science, 1997
The single event upset (SEU) sensitivity of certain types of linear microcircuits is strongly affected by bias conditions. For these devices, a model of upset mechanism and a method for SEU control have been suggested.
S D Pinkerton, K B Crawford, M C Maher   +2 more
exaly   +2 more sources

Single Event Upset (SEU) of Semiconductor Devices - A Summary of JPL Test Data

IEEE Transactions on Nuclear Science, 1983
A summary of the data on single event upset (bit flips) for sixt-y device types, having data storage elements, that were tested by JPL through May, 1982, is presented. The data were taken from fifteen accelerator tests with both protons and heavier ions.
Donald K. Nichols, William E. Price, Carl J. Malone   +2 more
exaly   +2 more sources

Designs and analysis of non-volatile memory cells for single event upset (SEU) tolerance

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2014
This paper proposes a comprehensive approach to the designs of low-power non-volatile (NV) memory cells and for attaining Single Event Upset (SEU) tolerance. Three low-power hardened NVSRAM cell designs are proposed; these designs increase the critical charge and decrease power consumption by providing a positive (virtual) ground level voltage ...
Wei Wei 0034, Fabrizio Lombardi, Kazuteru Namba   +2 more
openaire   +1 more source

A fault tolerant architecture to avoid the effects of Single Event Upset (SEU) in avionics applications

Measurement: Journal of the International Measurement Confederation, 2014
Abstract Commercial-Off-The-Shelf (COTS) Field Programmable Gate Array (FPGA) is becoming of increase interest in many field of high-tech applications for the possibility to implement low-cost solutions with simplicity and flexibility. Nevertheless, the presence of high energy incident particles (electrons, neutrons, protons and so on) can compromise
Lorenzo Ciani, Marcantonio Catelani
exaly   +3 more sources

Techniques of Microprocessor Testing and SEU (Single Event Upset)-Rate Prediction.

1986
Abstract : Several different approaches have been used in the past to assess the vulnerability of microprocessors to SEU. In this report we discuss the advantages and disadvantages of each of these test methods, and address the question of how the microprocessor test results can be used to estimate upset rate in space. Finally, as an application of the
Michael T. Marra, Wojciech A. Kolasinski, Rokutaro Koga   +2 more
openaire   +1 more source

Analysis of the Effects of Single Event Upsets (SEUs) on User Memory in FPGA Implemented Viterbi Decoders

2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2018
This paper analyzes the effects of single event upsets (SEUs) on the user memory of a Viterbi decoder implemented on an SRAM based FPGA. First, an FPGA Viterbi decoder implementation is used to study the structures that are mapped to user memory. Then, the SEUs tolerance capability for each of those structures is analyzed theoretically.
Zhen Gao 0001, Lina Yan, Jinhua Zhu, Ruishi Han, Pedro Reviriego   +4 more
openaire   +1 more source

Estimation of Single Event Upset (SEU) rates inside the SAA during the geomagnetic storm event of 15 May 2005

2021 IEEE International Conference on Wireless for Space and Extreme Environments (WiSEE), 2021
Kirolosse M Girgis, Shuichi Matsukiyo, Tohru Hada   +2 more
exaly   +2 more sources