Results 111 to 120 of about 264 (165)

Analysis and Evaluation of the Effects of Single Event Upsets (SEU s) on Memories in Polar Decoders

2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2021
Polar codes are used in 5G system for the transmission of control channels due to its excellent error correction capability for short sequence, and CRC assistant successive cancellation list (CA-SCL) decoders are commonly used in practical system. When applied in critical environment, e.g. space platform, the memories in the hardware polar decoder will
Zhen Gao 0005   +3 more
openaire   +1 more source

Single-Event-Upset (SEU) Awareness in FPGA Routing

2007 44th ACM/IEEE Design Automation Conference, 2007
The majority of configuration bits affecting a design are devoted to FPGA routing configuration. We present a SEU-aware routing algorithm that provides significant reduction in bridging faults caused by SEUs. Depending on the routing architecture switches, for MCNC benchmarks, the number of care bits can be reduced between 13% and 19% on average with ...
Shahin Golshan, Elaheh Bozorgzadeh
openaire   +1 more source

An Adaptive Single Event Upset (SEU)-Hardened Flip-Flop Design

2019 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), 2019
In this paper, a new radiation hardened flip-flop design technique is proposed. The structure provides an possibility that the D-type flip-flop can be configured as an Single Event Upset (SEU) hardened or non-hardened flip-flop in a circuit based on the logic states of the sensitive nodes with RC filtering structure being involved or not, considering ...
Zhongjie Guo
exaly   +2 more sources

Single-Event Upset (SEU) in a Dram with On-Chip Error Correction

IEEE Transactions on Nuclear Science, 1987
The results are given of the first SEU measurements ever reported on IC devices with on-chip error correction. This method of SEU abatement could revolutionize the design of SEU-immune electronic systems.
J. A. Zoutendyk   +4 more
exaly   +2 more sources

Error detection and correction of single event upset (SEU) tolerant latch

2012 IEEE 18th International On-Line Testing Symposium (IOLTS), 2012
Soft errors are a serious concern in state holder circuits at they can cause temporarily malfunctions. C-elements are one of the state holders that are widely used in asynchronous circuits. In this paper, our investigations focus on the vulnerability of different latch types based on C-elements with respect to soft errors.
Alex Yakovlev, A Bystrov
exaly   +2 more sources

Modeling dynamic stability of SRAMS in the presence of single event upsets (SEUs)

2008 IEEE International Symposium on Circuits and Systems, 2008
SRAM yield is very important from an economics viewpoint, because of the extensive use of memory in modern processors and SOCs. Therefore, SRAM stability analysis tools have become essential. SRAM stability analysis based on static noise margin (SNM) often results in pessimistic designs because SNM cannot capture the transient behavior of the noise ...
Rajesh Garg   +2 more
openaire   +1 more source

Design of a Single Event Upset (SEU) Mitigation Technique for Programmable Devices

7th International Symposium on Quality Electronic Design (ISQED'06), 2006
This paper presents a unique SEU (single event upset) mitigation technique based upon temporal data sampling for synchronous circuits and configuration bit storage for programmable devices. The design technique addresses both conventional static SEUs and SETs (single event transients) induced errors that can result in data loss for reconfigurable ...
Sajid Baloch   +2 more
openaire   +1 more source

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