Results 131 to 140 of about 264 (165)

An SEU (Single-event Upset) Mitigation Strategy on Read-Write Separation SRAM Cell for Low Power Consumption

2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT), 2020
SRAM for space applications continues to be disturbed by highly energetic charged particles along with technology node scaling, that is the single-event upset (SEU) in terms of time perspective. A 14T read-write separation SRAM cell in low power mode is proposed using radiation hardened by design (RHBD) technique, not only robust to SEU but also ...
Igor Kharitonov
exaly   +2 more sources

Selective triple Modular redundancy (STMR) based single-event upset (SEU) tolerant synthesis for FPGAs

IEEE Transactions on Nuclear Science, 2004
We present a design technique for hardening combinational circuits mapped onto Xilinx Virtex FPGAs against single-event upsets (SEUs). The signal probabilities of the lines can be used to detect SEU sensitive subcircuits of a given combinational circuit.
Srinivas Katkoori
exaly   +2 more sources

A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories

IEEE Transactions on Computers, 2016
This paper proposes a novel scheme for a low-power non-volatile (NV) memory that exploits a two-level arrangement for attaining single event/multiple bit upsets (SEU/MBU) tolerance. Low-power hardened NVSRAM cell designs are initially utilized at the first level; these designs increase the critical charge and decrease power consumption by providing a ...
Wei Wei 0034, Kazuteru Namba, Yong-Bin Kim, Fabrizio Lombardi   +3 more
openaire   +1 more source

System-Level Modeling and Analysis of the Vulnerability of a Processor to Single-Event Upsets (SEUs)

2019
In this chapter, an efficient system-level approach to model and analyze the propagation of SEUs in a simple processor is introduced. The high-level model of the processor is formalized as a Continuous-Time Markov Chain (CTMC). Probabilistic model checking (PMC) is utilized to exhaustively estimate the impact of SEUs on the behavior of the processor ...
Marwan Ammar, Ghaith Bany Hamad, Otmane Ait Mohamed, Yvon Savaria   +3 more
openaire   +2 more sources

Design of a novel 12T radiation hardened memory cell tolerant to single event upsets (SEU)

2017 2nd IEEE International Conference on Integrated Circuits and Microsystems (ICICM), 2017
A novel radiation hardened 12T memory cell (RH-12T) is proposed to address single event upset (SEU) problems in 65nm CMOS technology. It eliminates the possibility of a sensitive “0” storage node upset by surrounding the output nodes with NMOS, realizing a full resistance for any single node upset. Furthermore, less sensitive node pairs are obtained in
Chunyan Hu, Suge Yue, Shijin Lu
openaire   +1 more source

Experimental Determination of Single-Event Upset (SEU) as a Function of Collected Charge in Bipolar Integrated Circuits

IEEE Transactions on Nuclear Science, 1984
Single-Event Upset (SEU) in bipolar integrated circuits (ICs) is caused by charge collection from ion tracks in various regions of a bipolar transistor. This paper presents experimental data which have been obtained wherein the range-energy characteristics of heavy ions (Br) have been utilized to determine the cross section for soft-error generation as
J. A. Zoutendyk, C. J. Malone, L. S. Smith   +2 more
openaire   +1 more source

Neutron Induced Single Event Upset (SEU) Testing of Static Random Access Memory (SRAM) Devices

2014 IEEE Radiation Effects Data Workshop (REDW), 2014
Results of neutron induced single event upset (SEU) testing of two Synchronous Burst Static Random Access Memory (SRAM) devices, the Galvantech GVT71128G36 128K x 36 and the GSI GS816273CC 256K x 72, and the internal RAM (iRAM) in the Texas Instruments SM32C6713BGDPA20EP Digital Signal Processor (DSP) are described.
Michael J. Tostanoski, Terrence F. Deaton, Roy E. Strayer, Rudolf Goldflam, Travis Z. Fullem   +4 more
openaire   +1 more source

SEU (Single Event Upset) Vulnerability of the Zilog Z-80 and NSC-800 Microprocessors,

1986
Abstract : A detailed analysis of the SEU vulnerability of the Zilog Z-80 microprocessor is presented based upon data obtained with heavy ions and protons. The analysis demonstrates a method for separating upsets of the general purpose registers from upsets of the internal latches.
J. Cusick, C. King, W. A. Kolasinski, R. Koga   +3 more
openaire   +1 more source

Empirical Modeling of Single-Event Upset (SEU) in NMOS Depletion-Mode-Load Static RAM (SRAM) Chips

IEEE Transactions on Nuclear Science, 1986
A detailed experimental investigation of single-event upset (SEU) in static RAM (SRAM) chips fabricated using a family of high-performance NMOS (HMOS) depletion-mode-load process technologies, has been done. Empirical SEU models have been developed with the aid of heavy-ion data obtained with a three-stage tandem van de Graaff accelerator.
J. A. Zoutendyk, L. S. Smith, G. A. Soli, S. L. Smith, G. E. Atwood, P. Thieberger   +5 more
exaly   +2 more sources

Ion beam induced charge collection (IBICC) microscopy of ICs: relation to single event upsets (SEU)

Nuclear Instruments and Methods in Physics Research Section B: Beam Interactions with Materials and Atoms, 1993
Abstract Single event upset (SEU) imaging is a new diagnostic technique recently developed using Sandia's nuclear microprobe. This technique directly images, with micron resolution, those regions within an integrated circuit which are susceptible to ion-induced malfunctions. Such malfunctions are an increasing threat to space-based systems which make
K.M. Horn, B.L. Doyle, F.W. Sexton, J.S. Laird, A. Saint, M. Cholewa, G.J.F. Legge   +6 more
openaire   +1 more source